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https://github.com/c64scene-ar/llvm-6502.git
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f98f2ce29e
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
147 lines
5.1 KiB
TableGen
147 lines
5.1 KiB
TableGen
//===-- SIInstrFormats.td - SI Instruction Formats ------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// SI Instruction format definitions.
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//
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// Instructions with _32 take 32-bit operands.
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// Instructions with _64 take 64-bit operands.
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//
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// VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
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// encoding is the standard encoding, but instruction that make use of
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// any of the instruction modifiers must use the 64-bit encoding.
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//
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// Instructions with _e32 use the 32-bit encoding.
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// Instructions with _e64 use the 64-bit encoding.
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//
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//===----------------------------------------------------------------------===//
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class VOP3b_2IN <bits<9> op, string opName, RegisterClass dstClass,
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RegisterClass src0Class, RegisterClass src1Class,
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list<dag> pattern>
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: VOP3b <op, (outs dstClass:$vdst),
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(ins src0Class:$src0, src1Class:$src1, InstFlag:$src2, InstFlag:$sdst,
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InstFlag:$omod, InstFlag:$neg),
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opName, pattern
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>;
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class VOP3_1_32 <bits<9> op, string opName, list<dag> pattern>
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: VOP3b_2IN <op, opName, SReg_1, AllReg_32, VReg_32, pattern>;
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class VOP3_32 <bits<9> op, string opName, list<dag> pattern>
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: VOP3 <op, (outs VReg_32:$dst), (ins AllReg_32:$src0, VReg_32:$src1, VReg_32:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
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class VOP3_64 <bits<9> op, string opName, list<dag> pattern>
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: VOP3 <op, (outs VReg_64:$dst), (ins AllReg_64:$src0, VReg_64:$src1, VReg_64:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
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class SOP1_32 <bits<8> op, string opName, list<dag> pattern>
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: SOP1 <op, (outs SReg_32:$dst), (ins SReg_32:$src0), opName, pattern>;
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class SOP1_64 <bits<8> op, string opName, list<dag> pattern>
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: SOP1 <op, (outs SReg_64:$dst), (ins SReg_64:$src0), opName, pattern>;
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class SOP2_32 <bits<7> op, string opName, list<dag> pattern>
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: SOP2 <op, (outs SReg_32:$dst), (ins SReg_32:$src0, SReg_32:$src1), opName, pattern>;
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class SOP2_64 <bits<7> op, string opName, list<dag> pattern>
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: SOP2 <op, (outs SReg_64:$dst), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;
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class SOP2_VCC <bits<7> op, string opName, list<dag> pattern>
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: SOP2 <op, (outs SReg_1:$vcc), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;
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class VOP1_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
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string opName, list<dag> pattern> :
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VOP1 <
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op, (outs vrc:$dst), (ins arc:$src0), opName, pattern
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>;
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multiclass VOP1_32 <bits<8> op, string opName, list<dag> pattern> {
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def _e32: VOP1_Helper <op, VReg_32, AllReg_32, opName, pattern>;
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def _e64 : VOP3_32 <{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
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opName, []
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>;
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}
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multiclass VOP1_64 <bits<8> op, string opName, list<dag> pattern> {
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def _e32 : VOP1_Helper <op, VReg_64, AllReg_64, opName, pattern>;
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def _e64 : VOP3_64 <
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{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
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opName, []
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>;
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}
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class VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
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string opName, list<dag> pattern> :
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VOP2 <
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op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1), opName, pattern
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>;
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multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern> {
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def _e32 : VOP2_Helper <op, VReg_32, AllReg_32, opName, pattern>;
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def _e64 : VOP3_32 <{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
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opName, []
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>;
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}
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multiclass VOP2_64 <bits<6> op, string opName, list<dag> pattern> {
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def _e32: VOP2_Helper <op, VReg_64, AllReg_64, opName, pattern>;
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def _e64 : VOP3_64 <
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{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
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opName, []
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>;
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}
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class SOPK_32 <bits<5> op, string opName, list<dag> pattern>
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: SOPK <op, (outs SReg_32:$dst), (ins i16imm:$src0), opName, pattern>;
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class SOPK_64 <bits<5> op, string opName, list<dag> pattern>
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: SOPK <op, (outs SReg_64:$dst), (ins i16imm:$src0), opName, pattern>;
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class VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
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string opName, list<dag> pattern> :
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VOPC <
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op, (ins arc:$src0, vrc:$src1), opName, pattern
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>;
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multiclass VOPC_32 <bits<9> op, string opName, list<dag> pattern> {
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def _e32 : VOPC_Helper <
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{op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
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VReg_32, AllReg_32, opName, pattern
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>;
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def _e64 : VOP3_1_32 <
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op,
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opName, pattern
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>;
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}
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multiclass VOPC_64 <bits<8> op, string opName, list<dag> pattern> {
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def _e32 : VOPC_Helper <op, VReg_64, AllReg_64, opName, pattern>;
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def _e64 : VOP3_64 <
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{0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
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opName, []
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>;
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}
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class SOPC_32 <bits<7> op, string opName, list<dag> pattern>
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: SOPC <op, (outs SCCReg:$dst), (ins SReg_32:$src0, SReg_32:$src1), opName, pattern>;
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class SOPC_64 <bits<7> op, string opName, list<dag> pattern>
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: SOPC <op, (outs SCCReg:$dst), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;
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