mirror of
https://github.com/c64scene-ar/llvm-6502.git
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f5aeb1a8e4
with ConstantInt. This led to fixing a bug in TargetLowering.cpp using getValue instead of getAPIntValue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56159 91177308-0d34-0410-b5e6-96231b3b80d8
705 lines
22 KiB
C++
705 lines
22 KiB
C++
//===-- SPUISelDAGToDAG.cpp - CellSPU pattern matching inst selector ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a pattern matching instruction selector for the Cell SPU,
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// converting from a legalized dag to a SPU-target dag.
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//
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//===----------------------------------------------------------------------===//
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#include "SPU.h"
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#include "SPUTargetMachine.h"
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#include "SPUISelLowering.h"
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#include "SPUHazardRecognizers.h"
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#include "SPUFrameInfo.h"
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#include "SPURegisterNames.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Constants.h"
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#include "llvm/GlobalValue.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/Compiler.h"
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#include <queue>
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#include <set>
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using namespace llvm;
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namespace {
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//! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
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bool
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isI64IntS10Immediate(ConstantSDNode *CN)
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{
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return isS10Constant(CN->getSignExtended());
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}
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//! ConstantSDNode predicate for i32 sign-extended, 10-bit immediates
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bool
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isI32IntS10Immediate(ConstantSDNode *CN)
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{
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return isS10Constant(CN->getSignExtended());
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}
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#if 0
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//! SDNode predicate for sign-extended, 10-bit immediate values
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bool
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isI32IntS10Immediate(SDNode *N)
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{
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return (N->getOpcode() == ISD::Constant
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&& isI32IntS10Immediate(cast<ConstantSDNode>(N)));
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}
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#endif
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//! ConstantSDNode predicate for i32 unsigned 10-bit immediate values
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bool
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isI32IntU10Immediate(ConstantSDNode *CN)
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{
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return isU10Constant(CN->getSignExtended());
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}
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//! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
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bool
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isI16IntS10Immediate(ConstantSDNode *CN)
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{
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return isS10Constant(CN->getSignExtended());
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}
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//! SDNode predicate for i16 sign-extended, 10-bit immediate values
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bool
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isI16IntS10Immediate(SDNode *N)
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{
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return (N->getOpcode() == ISD::Constant
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&& isI16IntS10Immediate(cast<ConstantSDNode>(N)));
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}
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//! ConstantSDNode predicate for i16 unsigned 10-bit immediate values
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bool
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isI16IntU10Immediate(ConstantSDNode *CN)
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{
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return isU10Constant((short) CN->getZExtValue());
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}
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//! SDNode predicate for i16 sign-extended, 10-bit immediate values
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bool
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isI16IntU10Immediate(SDNode *N)
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{
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return (N->getOpcode() == ISD::Constant
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&& isI16IntU10Immediate(cast<ConstantSDNode>(N)));
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}
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//! ConstantSDNode predicate for signed 16-bit values
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/*!
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\arg CN The constant SelectionDAG node holding the value
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\arg Imm The returned 16-bit value, if returning true
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This predicate tests the value in \a CN to see whether it can be
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represented as a 16-bit, sign-extended quantity. Returns true if
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this is the case.
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*/
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bool
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isIntS16Immediate(ConstantSDNode *CN, short &Imm)
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{
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MVT vt = CN->getValueType(0);
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Imm = (short) CN->getZExtValue();
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if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
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return true;
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} else if (vt == MVT::i32) {
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int32_t i_val = (int32_t) CN->getZExtValue();
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short s_val = (short) i_val;
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return i_val == s_val;
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} else {
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int64_t i_val = (int64_t) CN->getZExtValue();
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short s_val = (short) i_val;
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return i_val == s_val;
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}
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return false;
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}
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//! SDNode predicate for signed 16-bit values.
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bool
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isIntS16Immediate(SDNode *N, short &Imm)
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{
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return (N->getOpcode() == ISD::Constant
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&& isIntS16Immediate(cast<ConstantSDNode>(N), Imm));
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}
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//! ConstantFPSDNode predicate for representing floats as 16-bit sign ext.
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static bool
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isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
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{
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MVT vt = FPN->getValueType(0);
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if (vt == MVT::f32) {
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int val = FloatToBits(FPN->getValueAPF().convertToFloat());
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int sval = (int) ((val << 16) >> 16);
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Imm = (short) val;
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return val == sval;
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}
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return false;
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}
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bool
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isHighLow(const SDValue &Op)
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{
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return (Op.getOpcode() == SPUISD::IndirectAddr
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&& ((Op.getOperand(0).getOpcode() == SPUISD::Hi
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&& Op.getOperand(1).getOpcode() == SPUISD::Lo)
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|| (Op.getOperand(0).getOpcode() == SPUISD::Lo
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&& Op.getOperand(1).getOpcode() == SPUISD::Hi)));
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}
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//===------------------------------------------------------------------===//
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//! MVT to "useful stuff" mapping structure:
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struct valtype_map_s {
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MVT VT;
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unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined)
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bool ldresult_imm; /// LDRESULT instruction requires immediate?
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int prefslot_byte; /// Byte offset of the "preferred" slot
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};
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const valtype_map_s valtype_map[] = {
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{ MVT::i1, 0, false, 3 },
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{ MVT::i8, SPU::ORBIr8, true, 3 },
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{ MVT::i16, SPU::ORHIr16, true, 2 },
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{ MVT::i32, SPU::ORIr32, true, 0 },
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{ MVT::i64, SPU::ORr64, false, 0 },
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{ MVT::f32, SPU::ORf32, false, 0 },
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{ MVT::f64, SPU::ORf64, false, 0 },
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// vector types... (sigh!)
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{ MVT::v16i8, 0, false, 0 },
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{ MVT::v8i16, 0, false, 0 },
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{ MVT::v4i32, 0, false, 0 },
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{ MVT::v2i64, 0, false, 0 },
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{ MVT::v4f32, 0, false, 0 },
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{ MVT::v2f64, 0, false, 0 }
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};
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const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
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const valtype_map_s *getValueTypeMapEntry(MVT VT)
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{
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const valtype_map_s *retval = 0;
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for (size_t i = 0; i < n_valtype_map; ++i) {
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if (valtype_map[i].VT == VT) {
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retval = valtype_map + i;
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break;
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}
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}
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#ifndef NDEBUG
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if (retval == 0) {
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cerr << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for "
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<< VT.getMVTString()
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<< "\n";
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abort();
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}
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#endif
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return retval;
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}
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}
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namespace {
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//===--------------------------------------------------------------------===//
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/// SPUDAGToDAGISel - Cell SPU-specific code to select SPU machine
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/// instructions for SelectionDAG operations.
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///
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class SPUDAGToDAGISel :
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public SelectionDAGISel
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{
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SPUTargetMachine &TM;
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SPUTargetLowering &SPUtli;
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unsigned GlobalBaseReg;
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public:
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explicit SPUDAGToDAGISel(SPUTargetMachine &tm) :
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SelectionDAGISel(*tm.getTargetLowering()),
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TM(tm),
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SPUtli(*tm.getTargetLowering())
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{}
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virtual bool runOnFunction(Function &Fn) {
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// Make sure we re-emit a set of the global base reg if necessary
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GlobalBaseReg = 0;
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SelectionDAGISel::runOnFunction(Fn);
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return true;
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}
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/// getI32Imm - Return a target constant with the specified value, of type
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/// i32.
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inline SDValue getI32Imm(uint32_t Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i32);
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}
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/// getI64Imm - Return a target constant with the specified value, of type
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/// i64.
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inline SDValue getI64Imm(uint64_t Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i64);
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}
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/// getSmallIPtrImm - Return a target constant of pointer type.
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inline SDValue getSmallIPtrImm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, SPUtli.getPointerTy());
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}
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/// Select - Convert the specified operand from a target-independent to a
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/// target-specific node if it hasn't already been changed.
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SDNode *Select(SDValue Op);
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//! Returns true if the address N is an A-form (local store) address
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bool SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
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SDValue &Index);
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//! D-form address predicate
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bool SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
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SDValue &Index);
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/// Alternate D-form address using i7 offset predicate
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bool SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
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SDValue &Base);
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/// D-form address selection workhorse
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bool DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Disp,
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SDValue &Base, int minOffset, int maxOffset);
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//! Address predicate if N can be expressed as an indexed [r+r] operation.
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bool SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
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SDValue &Index);
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions.
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virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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char ConstraintCode,
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std::vector<SDValue> &OutOps) {
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SDValue Op0, Op1;
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switch (ConstraintCode) {
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default: return true;
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case 'm': // memory
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if (!SelectDFormAddr(Op, Op, Op0, Op1)
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&& !SelectAFormAddr(Op, Op, Op0, Op1))
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SelectXFormAddr(Op, Op, Op0, Op1);
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break;
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case 'o': // offsetable
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if (!SelectDFormAddr(Op, Op, Op0, Op1)
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&& !SelectAFormAddr(Op, Op, Op0, Op1)) {
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Op0 = Op;
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AddToISelQueue(Op0); // r+0.
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Op1 = getSmallIPtrImm(0);
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}
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break;
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case 'v': // not offsetable
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#if 1
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assert(0 && "InlineAsmMemoryOperand 'v' constraint not handled.");
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#else
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SelectAddrIdxOnly(Op, Op, Op0, Op1);
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#endif
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break;
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}
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OutOps.push_back(Op0);
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OutOps.push_back(Op1);
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return false;
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}
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/// InstructionSelect - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelect();
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virtual const char *getPassName() const {
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return "Cell SPU DAG->DAG Pattern Instruction Selection";
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}
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/// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
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/// this target when scheduling the DAG.
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virtual HazardRecognizer *CreateTargetHazardRecognizer() {
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const TargetInstrInfo *II = TM.getInstrInfo();
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assert(II && "No InstrInfo?");
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return new SPUHazardRecognizer(*II);
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}
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// Include the pieces autogenerated from the target description.
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#include "SPUGenDAGISel.inc"
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};
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}
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/// InstructionSelect - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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void
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SPUDAGToDAGISel::InstructionSelect()
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{
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DEBUG(BB->dump());
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// Select target instructions for the DAG.
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SelectRoot();
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CurDAG->RemoveDeadNodes();
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}
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/*!
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\arg Op The ISD instructio operand
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\arg N The address to be tested
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\arg Base The base address
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\arg Index The base address index
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*/
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bool
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SPUDAGToDAGISel::SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
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SDValue &Index) {
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// These match the addr256k operand type:
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MVT OffsVT = MVT::i16;
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SDValue Zero = CurDAG->getTargetConstant(0, OffsVT);
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switch (N.getOpcode()) {
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case ISD::Constant:
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case ISD::ConstantPool:
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case ISD::GlobalAddress:
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cerr << "SPU SelectAFormAddr: Constant/Pool/Global not lowered.\n";
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abort();
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/*NOTREACHED*/
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case ISD::TargetConstant:
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case ISD::TargetGlobalAddress:
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case ISD::TargetJumpTable:
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cerr << "SPUSelectAFormAddr: Target Constant/Pool/Global not wrapped as "
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<< "A-form address.\n";
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abort();
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/*NOTREACHED*/
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case SPUISD::AFormAddr:
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// Just load from memory if there's only a single use of the location,
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// otherwise, this will get handled below with D-form offset addresses
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if (N.hasOneUse()) {
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SDValue Op0 = N.getOperand(0);
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switch (Op0.getOpcode()) {
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case ISD::TargetConstantPool:
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case ISD::TargetJumpTable:
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Base = Op0;
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Index = Zero;
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return true;
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case ISD::TargetGlobalAddress: {
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GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op0);
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GlobalValue *GV = GSDN->getGlobal();
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if (GV->getAlignment() == 16) {
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Base = Op0;
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Index = Zero;
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return true;
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}
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break;
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}
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}
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}
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break;
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}
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return false;
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}
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bool
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SPUDAGToDAGISel::SelectDForm2Addr(SDValue Op, SDValue N, SDValue &Disp,
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SDValue &Base) {
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const int minDForm2Offset = -(1 << 7);
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const int maxDForm2Offset = (1 << 7) - 1;
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return DFormAddressPredicate(Op, N, Disp, Base, minDForm2Offset,
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maxDForm2Offset);
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}
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/*!
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\arg Op The ISD instruction (ignored)
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\arg N The address to be tested
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\arg Base Base address register/pointer
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\arg Index Base address index
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Examine the input address by a base register plus a signed 10-bit
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displacement, [r+I10] (D-form address).
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\return true if \a N is a D-form address with \a Base and \a Index set
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to non-empty SDValue instances.
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*/
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bool
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SPUDAGToDAGISel::SelectDFormAddr(SDValue Op, SDValue N, SDValue &Base,
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SDValue &Index) {
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return DFormAddressPredicate(Op, N, Base, Index,
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SPUFrameInfo::minFrameOffset(),
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SPUFrameInfo::maxFrameOffset());
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}
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bool
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SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
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SDValue &Index, int minOffset,
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int maxOffset) {
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unsigned Opc = N.getOpcode();
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MVT PtrTy = SPUtli.getPointerTy();
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if (Opc == ISD::FrameIndex) {
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// Stack frame index must be less than 512 (divided by 16):
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FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N);
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int FI = int(FIN->getIndex());
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DEBUG(cerr << "SelectDFormAddr: ISD::FrameIndex = "
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<< FI << "\n");
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if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
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Base = CurDAG->getTargetConstant(0, PtrTy);
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Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
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return true;
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}
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} else if (Opc == ISD::ADD) {
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// Generated by getelementptr
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const SDValue Op0 = N.getOperand(0);
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const SDValue Op1 = N.getOperand(1);
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if ((Op0.getOpcode() == SPUISD::Hi && Op1.getOpcode() == SPUISD::Lo)
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|| (Op1.getOpcode() == SPUISD::Hi && Op0.getOpcode() == SPUISD::Lo)) {
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Base = CurDAG->getTargetConstant(0, PtrTy);
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Index = N;
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return true;
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} else if (Op1.getOpcode() == ISD::Constant
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|| Op1.getOpcode() == ISD::TargetConstant) {
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ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op1);
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int32_t offset = int32_t(CN->getSignExtended());
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if (Op0.getOpcode() == ISD::FrameIndex) {
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FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op0);
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int FI = int(FIN->getIndex());
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DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
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<< " frame index = " << FI << "\n");
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if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
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Base = CurDAG->getTargetConstant(offset, PtrTy);
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Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
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return true;
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}
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} else if (offset > minOffset && offset < maxOffset) {
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Base = CurDAG->getTargetConstant(offset, PtrTy);
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Index = Op0;
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return true;
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}
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} else if (Op0.getOpcode() == ISD::Constant
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|| Op0.getOpcode() == ISD::TargetConstant) {
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ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op0);
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int32_t offset = int32_t(CN->getSignExtended());
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if (Op1.getOpcode() == ISD::FrameIndex) {
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FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Op1);
|
|
int FI = int(FIN->getIndex());
|
|
DEBUG(cerr << "SelectDFormAddr: ISD::ADD offset = " << offset
|
|
<< " frame index = " << FI << "\n");
|
|
|
|
if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) {
|
|
Base = CurDAG->getTargetConstant(offset, PtrTy);
|
|
Index = CurDAG->getTargetFrameIndex(FI, PtrTy);
|
|
return true;
|
|
}
|
|
} else if (offset > minOffset && offset < maxOffset) {
|
|
Base = CurDAG->getTargetConstant(offset, PtrTy);
|
|
Index = Op1;
|
|
return true;
|
|
}
|
|
}
|
|
} else if (Opc == SPUISD::IndirectAddr) {
|
|
// Indirect with constant offset -> D-Form address
|
|
const SDValue Op0 = N.getOperand(0);
|
|
const SDValue Op1 = N.getOperand(1);
|
|
|
|
if (Op0.getOpcode() == SPUISD::Hi
|
|
&& Op1.getOpcode() == SPUISD::Lo) {
|
|
// (SPUindirect (SPUhi <arg>, 0), (SPUlo <arg>, 0))
|
|
Base = CurDAG->getTargetConstant(0, PtrTy);
|
|
Index = N;
|
|
return true;
|
|
} else if (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1)) {
|
|
int32_t offset = 0;
|
|
SDValue idxOp;
|
|
|
|
if (isa<ConstantSDNode>(Op1)) {
|
|
ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
|
|
offset = int32_t(CN->getSignExtended());
|
|
idxOp = Op0;
|
|
} else if (isa<ConstantSDNode>(Op0)) {
|
|
ConstantSDNode *CN = cast<ConstantSDNode>(Op0);
|
|
offset = int32_t(CN->getSignExtended());
|
|
idxOp = Op1;
|
|
}
|
|
|
|
if (offset >= minOffset && offset <= maxOffset) {
|
|
Base = CurDAG->getTargetConstant(offset, PtrTy);
|
|
Index = idxOp;
|
|
return true;
|
|
}
|
|
}
|
|
} else if (Opc == SPUISD::AFormAddr) {
|
|
Base = CurDAG->getTargetConstant(0, N.getValueType());
|
|
Index = N;
|
|
return true;
|
|
} else if (Opc == SPUISD::LDRESULT) {
|
|
Base = CurDAG->getTargetConstant(0, N.getValueType());
|
|
Index = N;
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
/*!
|
|
\arg Op The ISD instruction operand
|
|
\arg N The address operand
|
|
\arg Base The base pointer operand
|
|
\arg Index The offset/index operand
|
|
|
|
If the address \a N can be expressed as a [r + s10imm] address, returns false.
|
|
Otherwise, creates two operands, Base and Index that will become the [r+r]
|
|
address.
|
|
*/
|
|
bool
|
|
SPUDAGToDAGISel::SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
|
|
SDValue &Index) {
|
|
if (SelectAFormAddr(Op, N, Base, Index)
|
|
|| SelectDFormAddr(Op, N, Base, Index))
|
|
return false;
|
|
|
|
// All else fails, punt and use an X-form address:
|
|
Base = N.getOperand(0);
|
|
Index = N.getOperand(1);
|
|
return true;
|
|
}
|
|
|
|
//! Convert the operand from a target-independent to a target-specific node
|
|
/*!
|
|
*/
|
|
SDNode *
|
|
SPUDAGToDAGISel::Select(SDValue Op) {
|
|
SDNode *N = Op.getNode();
|
|
unsigned Opc = N->getOpcode();
|
|
int n_ops = -1;
|
|
unsigned NewOpc;
|
|
MVT OpVT = Op.getValueType();
|
|
SDValue Ops[8];
|
|
|
|
if (N->isMachineOpcode()) {
|
|
return NULL; // Already selected.
|
|
} else if (Opc == ISD::FrameIndex) {
|
|
// Selects to (add $sp, FI * stackSlotSize)
|
|
int FI =
|
|
SPUFrameInfo::FItoStackOffset(cast<FrameIndexSDNode>(N)->getIndex());
|
|
MVT PtrVT = SPUtli.getPointerTy();
|
|
|
|
// Adjust stack slot to actual offset in frame:
|
|
if (isS10Constant(FI)) {
|
|
DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with AIr32 $sp, "
|
|
<< FI
|
|
<< "\n");
|
|
NewOpc = SPU::AIr32;
|
|
Ops[0] = CurDAG->getRegister(SPU::R1, PtrVT);
|
|
Ops[1] = CurDAG->getTargetConstant(FI, PtrVT);
|
|
n_ops = 2;
|
|
} else {
|
|
DEBUG(cerr << "SPUDAGToDAGISel: Replacing FrameIndex with Ar32 $sp, "
|
|
<< FI
|
|
<< "\n");
|
|
NewOpc = SPU::Ar32;
|
|
Ops[0] = CurDAG->getRegister(SPU::R1, PtrVT);
|
|
Ops[1] = CurDAG->getConstant(FI, PtrVT);
|
|
n_ops = 2;
|
|
|
|
AddToISelQueue(Ops[1]);
|
|
}
|
|
} else if (Opc == ISD::ZERO_EXTEND) {
|
|
// (zero_extend:i16 (and:i8 <arg>, <const>))
|
|
const SDValue &Op1 = N->getOperand(0);
|
|
|
|
if (Op.getValueType() == MVT::i16 && Op1.getValueType() == MVT::i8) {
|
|
if (Op1.getOpcode() == ISD::AND) {
|
|
// Fold this into a single ANDHI. This is often seen in expansions of i1
|
|
// to i8, then i8 to i16 in logical/branching operations.
|
|
DEBUG(cerr << "CellSPU: Coalescing (zero_extend:i16 (and:i8 "
|
|
"<arg>, <const>))\n");
|
|
NewOpc = SPU::ANDHIi8i16;
|
|
Ops[0] = Op1.getOperand(0);
|
|
Ops[1] = Op1.getOperand(1);
|
|
n_ops = 2;
|
|
}
|
|
}
|
|
} else if (Opc == SPUISD::LDRESULT) {
|
|
// Custom select instructions for LDRESULT
|
|
MVT VT = N->getValueType(0);
|
|
SDValue Arg = N->getOperand(0);
|
|
SDValue Chain = N->getOperand(1);
|
|
SDNode *Result;
|
|
const valtype_map_s *vtm = getValueTypeMapEntry(VT);
|
|
|
|
if (vtm->ldresult_ins == 0) {
|
|
cerr << "LDRESULT for unsupported type: "
|
|
<< VT.getMVTString()
|
|
<< "\n";
|
|
abort();
|
|
}
|
|
|
|
AddToISelQueue(Arg);
|
|
Opc = vtm->ldresult_ins;
|
|
if (vtm->ldresult_imm) {
|
|
SDValue Zero = CurDAG->getTargetConstant(0, VT);
|
|
|
|
AddToISelQueue(Zero);
|
|
Result = CurDAG->getTargetNode(Opc, VT, MVT::Other, Arg, Zero, Chain);
|
|
} else {
|
|
Result = CurDAG->getTargetNode(Opc, MVT::Other, Arg, Arg, Chain);
|
|
}
|
|
|
|
Chain = SDValue(Result, 1);
|
|
AddToISelQueue(Chain);
|
|
|
|
return Result;
|
|
} else if (Opc == SPUISD::IndirectAddr) {
|
|
SDValue Op0 = Op.getOperand(0);
|
|
if (Op0.getOpcode() == SPUISD::LDRESULT) {
|
|
/* || Op0.getOpcode() == SPUISD::AFormAddr) */
|
|
// (IndirectAddr (LDRESULT, imm))
|
|
SDValue Op1 = Op.getOperand(1);
|
|
MVT VT = Op.getValueType();
|
|
|
|
DEBUG(cerr << "CellSPU: IndirectAddr(LDRESULT, imm):\nOp0 = ");
|
|
DEBUG(Op.getOperand(0).getNode()->dump(CurDAG));
|
|
DEBUG(cerr << "\nOp1 = ");
|
|
DEBUG(Op.getOperand(1).getNode()->dump(CurDAG));
|
|
DEBUG(cerr << "\n");
|
|
|
|
if (Op1.getOpcode() == ISD::Constant) {
|
|
ConstantSDNode *CN = cast<ConstantSDNode>(Op1);
|
|
Op1 = CurDAG->getTargetConstant(CN->getZExtValue(), VT);
|
|
NewOpc = (isI32IntS10Immediate(CN) ? SPU::AIr32 : SPU::Ar32);
|
|
AddToISelQueue(Op0);
|
|
AddToISelQueue(Op1);
|
|
Ops[0] = Op0;
|
|
Ops[1] = Op1;
|
|
n_ops = 2;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (n_ops > 0) {
|
|
if (N->hasOneUse())
|
|
return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops);
|
|
else
|
|
return CurDAG->getTargetNode(NewOpc, OpVT, Ops, n_ops);
|
|
} else
|
|
return SelectCode(Op);
|
|
}
|
|
|
|
/// createPPCISelDag - This pass converts a legalized DAG into a
|
|
/// SPU-specific DAG, ready for instruction scheduling.
|
|
///
|
|
FunctionPass *llvm::createSPUISelDag(SPUTargetMachine &TM) {
|
|
return new SPUDAGToDAGISel(TM);
|
|
}
|