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9996663fc6
flags (ARMISD::CMPNZ) and comparisons that use all flags (ARMISD::CMP). - Defines the instructions: TST, TEQ (ARM) and TST (Thumb). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35573 91177308-0d34-0410-b5e6-96231b3b80d8
567 lines
20 KiB
TableGen
567 lines
20 KiB
TableGen
//===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under the
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// University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Thumb instruction set.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Thumb specific DAG Nodes.
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//
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def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
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[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
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// TI - Thumb instruction.
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// ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
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class ThumbPat<dag pattern, dag result> : Pat<pattern, result> {
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list<Predicate> Predicates = [IsThumb];
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}
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class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
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list<Predicate> Predicates = [IsThumb, HasV5T];
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}
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class ThumbI<dag ops, AddrMode am, SizeFlagVal sz,
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string asm, string cstr, list<dag> pattern>
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// FIXME: Set all opcodes to 0 for now.
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: InstARM<0, am, sz, IndexModeNone, ops, asm, cstr> {
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let Pattern = pattern;
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list<Predicate> Predicates = [IsThumb];
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}
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class TI<dag ops, string asm, list<dag> pattern>
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: ThumbI<ops, AddrModeNone, Size2Bytes, asm, "", pattern>;
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class TI1<dag ops, string asm, list<dag> pattern>
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: ThumbI<ops, AddrModeT1, Size2Bytes, asm, "", pattern>;
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class TI2<dag ops, string asm, list<dag> pattern>
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: ThumbI<ops, AddrModeT2, Size2Bytes, asm, "", pattern>;
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class TI4<dag ops, string asm, list<dag> pattern>
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: ThumbI<ops, AddrModeT4, Size2Bytes, asm, "", pattern>;
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class TIs<dag ops, string asm, list<dag> pattern>
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: ThumbI<ops, AddrModeTs, Size2Bytes, asm, "", pattern>;
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// Two-address instructions
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class TIt<dag ops, string asm, list<dag> pattern>
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: ThumbI<ops, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
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// BL, BLX(1) are translated by assembler into two instructions
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class TIx2<dag ops, string asm, list<dag> pattern>
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: ThumbI<ops, AddrModeNone, Size4Bytes, asm, "", pattern>;
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// BR_JT instructions
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class TJTI<dag ops, string asm, list<dag> pattern>
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: ThumbI<ops, AddrModeNone, SizeSpecial, asm, "", pattern>;
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def imm_neg_XFORM : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(-(int)N->getValue(), MVT::i32);
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}]>;
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def imm_comp_XFORM : SDNodeXForm<imm, [{
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return CurDAG->getTargetConstant(~((uint32_t)N->getValue()), MVT::i32);
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}]>;
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/// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
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def imm0_7 : PatLeaf<(i32 imm), [{
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return (uint32_t)N->getValue() < 8;
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}]>;
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def imm0_7_neg : PatLeaf<(i32 imm), [{
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return (uint32_t)-N->getValue() < 8;
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}], imm_neg_XFORM>;
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def imm0_255 : PatLeaf<(i32 imm), [{
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return (uint32_t)N->getValue() < 256;
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}]>;
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def imm0_255_comp : PatLeaf<(i32 imm), [{
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return ~((uint32_t)N->getValue()) < 256;
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}]>;
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def imm8_255 : PatLeaf<(i32 imm), [{
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return (uint32_t)N->getValue() >= 8 && (uint32_t)N->getValue() < 256;
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}]>;
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def imm8_255_neg : PatLeaf<(i32 imm), [{
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unsigned Val = -N->getValue();
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return Val >= 8 && Val < 256;
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}], imm_neg_XFORM>;
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// Break imm's up into two pieces: an immediate + a left shift.
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// This uses thumb_immshifted to match and thumb_immshifted_val and
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// thumb_immshifted_shamt to get the val/shift pieces.
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def thumb_immshifted : PatLeaf<(imm), [{
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return ARM_AM::isThumbImmShiftedVal((unsigned)N->getValue());
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}]>;
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def thumb_immshifted_val : SDNodeXForm<imm, [{
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unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getValue());
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return CurDAG->getTargetConstant(V, MVT::i32);
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}]>;
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def thumb_immshifted_shamt : SDNodeXForm<imm, [{
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unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getValue());
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return CurDAG->getTargetConstant(V, MVT::i32);
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}]>;
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// Define Thumb specific addressing modes.
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// t_addrmode_rr := reg + reg
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//
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def t_addrmode_rr : Operand<i32>,
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ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
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let PrintMethod = "printThumbAddrModeRROperand";
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let MIOperandInfo = (ops GPR:$base, GPR:$offsreg);
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}
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// t_addrmode_s4 := reg + reg
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// reg + imm5 * 4
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//
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def t_addrmode_s4 : Operand<i32>,
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ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
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let PrintMethod = "printThumbAddrModeS4Operand";
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let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg);
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}
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// t_addrmode_s2 := reg + reg
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// reg + imm5 * 2
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//
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def t_addrmode_s2 : Operand<i32>,
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ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
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let PrintMethod = "printThumbAddrModeS2Operand";
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let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg);
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}
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// t_addrmode_s1 := reg + reg
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// reg + imm5
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//
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def t_addrmode_s1 : Operand<i32>,
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ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
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let PrintMethod = "printThumbAddrModeS1Operand";
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let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg);
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}
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// t_addrmode_sp := sp + imm8 * 4
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//
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def t_addrmode_sp : Operand<i32>,
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ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
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let PrintMethod = "printThumbAddrModeSPOperand";
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let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
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}
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//===----------------------------------------------------------------------===//
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// Miscellaneous Instructions.
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//
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def tPICADD : TIt<(ops GPR:$dst, GPR:$lhs, pclabel:$cp),
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"$cp:\n\tadd $dst, pc",
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[(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
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//===----------------------------------------------------------------------===//
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// Control Flow Instructions.
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//
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let isReturn = 1, isTerminator = 1 in {
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def tBX_RET : TI<(ops), "bx lr", [(ARMretflag)]>;
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// Alternative return instruction used by vararg functions.
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def tBX_RET_vararg : TI<(ops GPR:$dst), "bx $dst", []>;
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}
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// FIXME: remove when we have a way to marking a MI with these properties.
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let isLoad = 1, isReturn = 1, isTerminator = 1 in
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def tPOP_RET : TI<(ops reglist:$dst1, variable_ops),
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"pop $dst1", []>;
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let isCall = 1, noResults = 1,
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Defs = [R0, R1, R2, R3, LR,
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D0, D1, D2, D3, D4, D5, D6, D7] in {
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def tBL : TIx2<(ops i32imm:$func, variable_ops),
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"bl ${func:call}",
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[(ARMtcall tglobaladdr:$func)]>;
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// ARMv5T and above
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def tBLXi : TIx2<(ops i32imm:$func, variable_ops),
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"blx ${func:call}",
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[(ARMcall tglobaladdr:$func)]>, Requires<[HasV5T]>;
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def tBLXr : TI<(ops GPR:$dst, variable_ops),
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"blx $dst",
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[(ARMtcall GPR:$dst)]>, Requires<[HasV5T]>;
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// ARMv4T
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def tBX : TIx2<(ops GPR:$dst, variable_ops),
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"cpy lr, pc\n\tbx $dst",
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[(ARMcall_nolink GPR:$dst)]>;
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}
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let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
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def tB : TI<(ops brtarget:$dst), "b $dst", [(br bb:$dst)]>;
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// Far jump
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def tBfar : TIx2<(ops brtarget:$dst), "bl $dst\t@ far jump", []>;
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def tBR_JTr : TJTI<(ops GPR:$dst, jtblock_operand:$jt, i32imm:$id),
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"cpy pc, $dst \n\t.align\t2\n$jt",
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[(ARMbrjt GPR:$dst, tjumptable:$jt, imm:$id)]>;
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}
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let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in
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def tBcc : TI<(ops brtarget:$dst, CCOp:$cc), "b$cc $dst",
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[(ARMbrcond bb:$dst, imm:$cc)]>;
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//===----------------------------------------------------------------------===//
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// Load Store Instructions.
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//
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let isLoad = 1 in {
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def tLDR : TI4<(ops GPR:$dst, t_addrmode_s4:$addr),
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"ldr $dst, $addr",
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[(set GPR:$dst, (load t_addrmode_s4:$addr))]>;
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def tLDRB : TI1<(ops GPR:$dst, t_addrmode_s1:$addr),
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"ldrb $dst, $addr",
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[(set GPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
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def tLDRH : TI2<(ops GPR:$dst, t_addrmode_s2:$addr),
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"ldrh $dst, $addr",
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[(set GPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
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def tLDRSB : TI1<(ops GPR:$dst, t_addrmode_rr:$addr),
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"ldrsb $dst, $addr",
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[(set GPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
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def tLDRSH : TI2<(ops GPR:$dst, t_addrmode_rr:$addr),
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"ldrsh $dst, $addr",
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[(set GPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
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def tLDRspi : TIs<(ops GPR:$dst, t_addrmode_sp:$addr),
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"ldr $dst, $addr",
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[(set GPR:$dst, (load t_addrmode_sp:$addr))]>;
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// Special instruction for restore. It cannot clobber condition register
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// when it's expanded by eliminateCallFramePseudoInstr().
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def tRestore : TIs<(ops GPR:$dst, t_addrmode_sp:$addr),
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"ldr $dst, $addr", []>;
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// Load tconstpool
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def tLDRpci : TIs<(ops GPR:$dst, i32imm:$addr),
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"ldr $dst, $addr",
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[(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
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// Special LDR for loads from non-pc-relative constpools.
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let isReMaterializable = 1 in
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def tLDRcp : TIs<(ops GPR:$dst, i32imm:$addr),
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"ldr $dst, $addr", []>;
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} // isLoad
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let isStore = 1 in {
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def tSTR : TI4<(ops GPR:$src, t_addrmode_s4:$addr),
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"str $src, $addr",
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[(store GPR:$src, t_addrmode_s4:$addr)]>;
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def tSTRB : TI1<(ops GPR:$src, t_addrmode_s1:$addr),
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"strb $src, $addr",
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[(truncstorei8 GPR:$src, t_addrmode_s1:$addr)]>;
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def tSTRH : TI2<(ops GPR:$src, t_addrmode_s2:$addr),
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"strh $src, $addr",
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[(truncstorei16 GPR:$src, t_addrmode_s2:$addr)]>;
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def tSTRspi : TIs<(ops GPR:$src, t_addrmode_sp:$addr),
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"str $src, $addr",
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[(store GPR:$src, t_addrmode_sp:$addr)]>;
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// Special instruction for spill. It cannot clobber condition register
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// when it's expanded by eliminateCallFramePseudoInstr().
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def tSpill : TIs<(ops GPR:$src, t_addrmode_sp:$addr),
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"str $src, $addr", []>;
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}
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//===----------------------------------------------------------------------===//
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// Load / store multiple Instructions.
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//
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// TODO: A7-44: LDMIA - load multiple
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let isLoad = 1 in
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def tPOP : TI<(ops reglist:$dst1, variable_ops),
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"pop $dst1", []>;
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let isStore = 1 in
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def tPUSH : TI<(ops reglist:$src1, variable_ops),
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"push $src1", []>;
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//===----------------------------------------------------------------------===//
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// Arithmetic Instructions.
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//
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// Add with carry
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def tADC : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
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"adc $dst, $rhs",
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[(set GPR:$dst, (adde GPR:$lhs, GPR:$rhs))]>;
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def tADDS : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
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"add $dst, $lhs, $rhs",
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[(set GPR:$dst, (addc GPR:$lhs, GPR:$rhs))]>;
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def tADDi3 : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
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"add $dst, $lhs, $rhs",
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[(set GPR:$dst, (add GPR:$lhs, imm0_7:$rhs))]>;
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def tADDi8 : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
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"add $dst, $rhs",
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[(set GPR:$dst, (add GPR:$lhs, imm8_255:$rhs))]>;
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def tADDrr : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
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"add $dst, $lhs, $rhs",
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[(set GPR:$dst, (add GPR:$lhs, GPR:$rhs))]>;
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def tADDhirr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
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"add $dst, $rhs", []>;
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def tADDrPCi : TI<(ops GPR:$dst, i32imm:$rhs),
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"add $dst, pc, $rhs * 4", []>;
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def tADDrSPi : TI<(ops GPR:$dst, GPR:$sp, i32imm:$rhs),
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"add $dst, $sp, $rhs * 4", []>;
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def tADDspi : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
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"add $dst, $rhs * 4", []>;
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def tAND : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
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"and $dst, $rhs",
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[(set GPR:$dst, (and GPR:$lhs, GPR:$rhs))]>;
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def tASRri : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
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"asr $dst, $lhs, $rhs",
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[(set GPR:$dst, (sra GPR:$lhs, imm:$rhs))]>;
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def tASRrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
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"asr $dst, $rhs",
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[(set GPR:$dst, (sra GPR:$lhs, GPR:$rhs))]>;
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def tBIC : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
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"bic $dst, $rhs",
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[(set GPR:$dst, (and GPR:$lhs, (not GPR:$rhs)))]>;
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def tCMN : TI<(ops GPR:$lhs, GPR:$rhs),
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"cmn $lhs, $rhs",
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[(ARMcmp GPR:$lhs, (ineg GPR:$rhs))]>;
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def tCMPi8 : TI<(ops GPR:$lhs, i32imm:$rhs),
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"cmp $lhs, $rhs",
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[(ARMcmp GPR:$lhs, imm0_255:$rhs)]>;
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def tCMPr : TI<(ops GPR:$lhs, GPR:$rhs),
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"cmp $lhs, $rhs",
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[(ARMcmp GPR:$lhs, GPR:$rhs)]>;
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def tTST : TI<(ops GPR:$lhs, GPR:$rhs),
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"tst $lhs, $rhs",
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[(ARMcmpNZ (and GPR:$lhs, GPR:$rhs), 0)]>;
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def tCMNNZ : TI<(ops GPR:$lhs, GPR:$rhs),
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"cmn $lhs, $rhs",
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[(ARMcmpNZ GPR:$lhs, (ineg GPR:$rhs))]>;
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def tCMPNZi8 : TI<(ops GPR:$lhs, i32imm:$rhs),
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"cmp $lhs, $rhs",
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[(ARMcmpNZ GPR:$lhs, imm0_255:$rhs)]>;
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def tCMPNZr : TI<(ops GPR:$lhs, GPR:$rhs),
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"cmp $lhs, $rhs",
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[(ARMcmpNZ GPR:$lhs, GPR:$rhs)]>;
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// TODO: A7-37: CMP(3) - cmp hi regs
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def tEOR : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
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"eor $dst, $rhs",
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[(set GPR:$dst, (xor GPR:$lhs, GPR:$rhs))]>;
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def tLSLri : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
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"lsl $dst, $lhs, $rhs",
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[(set GPR:$dst, (shl GPR:$lhs, imm:$rhs))]>;
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def tLSLrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
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"lsl $dst, $rhs",
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[(set GPR:$dst, (shl GPR:$lhs, GPR:$rhs))]>;
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def tLSRri : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
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"lsr $dst, $lhs, $rhs",
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[(set GPR:$dst, (srl GPR:$lhs, imm:$rhs))]>;
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def tLSRrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
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"lsr $dst, $rhs",
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[(set GPR:$dst, (srl GPR:$lhs, GPR:$rhs))]>;
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// FIXME: This is not rematerializable because mov changes the condition code.
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def tMOVi8 : TI<(ops GPR:$dst, i32imm:$src),
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"mov $dst, $src",
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[(set GPR:$dst, imm0_255:$src)]>;
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// TODO: A7-73: MOV(2) - mov setting flag.
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// Note: MOV(2) of two low regs updates the flags, so we emit this as 'cpy',
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// which is MOV(3). This also supports high registers.
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def tMOVr : TI<(ops GPR:$dst, GPR:$src),
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"cpy $dst, $src", []>;
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def tMUL : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
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|
"mul $dst, $rhs",
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[(set GPR:$dst, (mul GPR:$lhs, GPR:$rhs))]>;
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|
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def tMVN : TI<(ops GPR:$dst, GPR:$src),
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"mvn $dst, $src",
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[(set GPR:$dst, (not GPR:$src))]>;
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|
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def tNEG : TI<(ops GPR:$dst, GPR:$src),
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|
"neg $dst, $src",
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|
[(set GPR:$dst, (ineg GPR:$src))]>;
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|
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def tORR : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
|
|
"orr $dst, $rhs",
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[(set GPR:$dst, (or GPR:$lhs, GPR:$rhs))]>;
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|
|
|
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def tREV : TI<(ops GPR:$dst, GPR:$src),
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|
"rev $dst, $src",
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|
[(set GPR:$dst, (bswap GPR:$src))]>,
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|
Requires<[IsThumb, HasV6]>;
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|
|
|
def tREV16 : TI<(ops GPR:$dst, GPR:$src),
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|
"rev16 $dst, $src",
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|
[(set GPR:$dst,
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|
(or (and (srl GPR:$src, 8), 0xFF),
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|
(or (and (shl GPR:$src, 8), 0xFF00),
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|
(or (and (srl GPR:$src, 8), 0xFF0000),
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|
(and (shl GPR:$src, 8), 0xFF000000)))))]>,
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|
Requires<[IsThumb, HasV6]>;
|
|
|
|
def tREVSH : TI<(ops GPR:$dst, GPR:$src),
|
|
"revsh $dst, $src",
|
|
[(set GPR:$dst,
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|
(sext_inreg
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|
(or (srl (and GPR:$src, 0xFFFF), 8),
|
|
(shl GPR:$src, 8)), i16))]>,
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|
Requires<[IsThumb, HasV6]>;
|
|
|
|
def tROR : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
|
|
"ror $dst, $rhs",
|
|
[(set GPR:$dst, (rotr GPR:$lhs, GPR:$rhs))]>;
|
|
|
|
|
|
// Subtract with carry
|
|
def tSBC : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
|
|
"sbc $dst, $rhs",
|
|
[(set GPR:$dst, (sube GPR:$lhs, GPR:$rhs))]>;
|
|
|
|
def tSUBS : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
|
|
"sub $dst, $lhs, $rhs",
|
|
[(set GPR:$dst, (subc GPR:$lhs, GPR:$rhs))]>;
|
|
|
|
|
|
// TODO: A7-96: STMIA - store multiple.
|
|
|
|
def tSUBi3 : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
|
|
"sub $dst, $lhs, $rhs",
|
|
[(set GPR:$dst, (add GPR:$lhs, imm0_7_neg:$rhs))]>;
|
|
|
|
def tSUBi8 : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
|
|
"sub $dst, $rhs",
|
|
[(set GPR:$dst, (add GPR:$lhs, imm8_255_neg:$rhs))]>;
|
|
|
|
def tSUBrr : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
|
|
"sub $dst, $lhs, $rhs",
|
|
[(set GPR:$dst, (sub GPR:$lhs, GPR:$rhs))]>;
|
|
|
|
def tSUBspi : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
|
|
"sub $dst, $rhs * 4", []>;
|
|
|
|
def tSXTB : TI<(ops GPR:$dst, GPR:$src),
|
|
"sxtb $dst, $src",
|
|
[(set GPR:$dst, (sext_inreg GPR:$src, i8))]>,
|
|
Requires<[IsThumb, HasV6]>;
|
|
def tSXTH : TI<(ops GPR:$dst, GPR:$src),
|
|
"sxth $dst, $src",
|
|
[(set GPR:$dst, (sext_inreg GPR:$src, i16))]>,
|
|
Requires<[IsThumb, HasV6]>;
|
|
|
|
|
|
def tUXTB : TI<(ops GPR:$dst, GPR:$src),
|
|
"uxtb $dst, $src",
|
|
[(set GPR:$dst, (and GPR:$src, 0xFF))]>,
|
|
Requires<[IsThumb, HasV6]>;
|
|
def tUXTH : TI<(ops GPR:$dst, GPR:$src),
|
|
"uxth $dst, $src",
|
|
[(set GPR:$dst, (and GPR:$src, 0xFFFF))]>,
|
|
Requires<[IsThumb, HasV6]>;
|
|
|
|
|
|
// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
|
|
// Expanded by the scheduler into a branch sequence.
|
|
let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
|
|
def tMOVCCr :
|
|
PseudoInst<(ops GPR:$dst, GPR:$false, GPR:$true, CCOp:$cc),
|
|
"@ tMOVCCr $cc",
|
|
[(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))]>;
|
|
|
|
// tLEApcrel - Load a pc-relative address into a register without offending the
|
|
// assembler.
|
|
def tLEApcrel : TIx2<(ops GPR:$dst, i32imm:$label),
|
|
!strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
|
|
"${:private}PCRELL${:uid}+6))\n"),
|
|
!strconcat("\tmov $dst, #PCRELV${:uid}\n",
|
|
"${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
|
|
[]>;
|
|
|
|
def tLEApcrelJT : TIx2<(ops GPR:$dst, i32imm:$label, i32imm:$id),
|
|
!strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
|
|
"${:private}PCRELL${:uid}+4))\n"),
|
|
!strconcat("\tmov $dst, #PCRELV${:uid}\n",
|
|
"${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
|
|
[]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Non-Instruction Patterns
|
|
//
|
|
|
|
// ConstantPool, GlobalAddress
|
|
def : ThumbPat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
|
|
def : ThumbPat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
|
|
|
|
// JumpTable
|
|
def : ThumbPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
|
|
(tLEApcrelJT tjumptable:$dst, imm:$id)>;
|
|
|
|
// Direct calls
|
|
def : ThumbPat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>;
|
|
def : ThumbV5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>;
|
|
|
|
// Indirect calls to ARM routines
|
|
def : ThumbV5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>;
|
|
|
|
// zextload i1 -> zextload i8
|
|
def : ThumbPat<(zextloadi1 t_addrmode_s1:$addr),
|
|
(tLDRB t_addrmode_s1:$addr)>;
|
|
|
|
// extload -> zextload
|
|
def : ThumbPat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
|
|
def : ThumbPat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
|
|
def : ThumbPat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
|
|
|
|
// truncstore i1 -> truncstore i8
|
|
def : ThumbPat<(truncstorei1 GPR:$src, t_addrmode_s1:$dst),
|
|
(tSTRB GPR:$src, t_addrmode_s1:$dst)>;
|
|
|
|
// Large immediate handling.
|
|
|
|
// Two piece imms.
|
|
def : ThumbPat<(i32 thumb_immshifted:$src),
|
|
(tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
|
|
(thumb_immshifted_shamt imm:$src))>;
|
|
|
|
def : ThumbPat<(i32 imm0_255_comp:$src),
|
|
(tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
|