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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139816 91177308-0d34-0410-b5e6-96231b3b80d8
155 lines
5.6 KiB
C++
155 lines
5.6 KiB
C++
//===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the X86 specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#include "X86TargetMachine.h"
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#include "X86.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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extern "C" void LLVMInitializeX86Target() {
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// Register the target.
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RegisterTargetMachine<X86_32TargetMachine> X(TheX86_32Target);
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RegisterTargetMachine<X86_64TargetMachine> Y(TheX86_64Target);
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}
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X86_32TargetMachine::X86_32TargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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Reloc::Model RM, CodeModel::Model CM)
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: X86TargetMachine(T, TT, CPU, FS, RM, CM, false),
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DataLayout(getSubtargetImpl()->isTargetDarwin() ?
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"e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-n8:16:32" :
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(getSubtargetImpl()->isTargetCygMing() ||
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getSubtargetImpl()->isTargetWindows()) ?
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"e-p:32:32-f64:64:64-i64:64:64-f80:32:32-f128:128:128-n8:16:32" :
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"e-p:32:32-f64:32:64-i64:32:64-f80:32:32-f128:128:128-n8:16:32"),
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InstrInfo(*this),
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TSInfo(*this),
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TLInfo(*this),
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JITInfo(*this) {
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}
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X86_64TargetMachine::X86_64TargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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Reloc::Model RM, CodeModel::Model CM)
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: X86TargetMachine(T, TT, CPU, FS, RM, CM, true),
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DataLayout("e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-n8:16:32:64"),
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InstrInfo(*this),
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TSInfo(*this),
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TLInfo(*this),
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JITInfo(*this) {
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}
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/// X86TargetMachine ctor - Create an X86 target.
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///
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X86TargetMachine::X86TargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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Reloc::Model RM, CodeModel::Model CM,
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bool is64Bit)
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: LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
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Subtarget(TT, CPU, FS, StackAlignmentOverride, is64Bit),
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FrameLowering(*this, Subtarget),
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ELFWriterInfo(is64Bit, true) {
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// Determine the PICStyle based on the target selected.
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if (getRelocationModel() == Reloc::Static) {
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// Unless we're in PIC or DynamicNoPIC mode, set the PIC style to None.
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Subtarget.setPICStyle(PICStyles::None);
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} else if (Subtarget.is64Bit()) {
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// PIC in 64 bit mode is always rip-rel.
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Subtarget.setPICStyle(PICStyles::RIPRel);
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} else if (Subtarget.isTargetCygMing()) {
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Subtarget.setPICStyle(PICStyles::None);
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} else if (Subtarget.isTargetDarwin()) {
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if (getRelocationModel() == Reloc::PIC_)
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Subtarget.setPICStyle(PICStyles::StubPIC);
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else {
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assert(getRelocationModel() == Reloc::DynamicNoPIC);
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Subtarget.setPICStyle(PICStyles::StubDynamicNoPIC);
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}
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} else if (Subtarget.isTargetELF()) {
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Subtarget.setPICStyle(PICStyles::GOT);
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}
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// default to hard float ABI
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if (FloatABIType == FloatABI::Default)
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FloatABIType = FloatABI::Hard;
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}
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//===----------------------------------------------------------------------===//
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// Command line options for x86
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//===----------------------------------------------------------------------===//
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static cl::opt<bool>
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UseVZeroUpper("x86-use-vzeroupper",
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cl::desc("Minimize AVX to SSE transition penalty"),
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cl::init(false));
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//===----------------------------------------------------------------------===//
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// Pass Pipeline Configuration
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//===----------------------------------------------------------------------===//
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bool X86TargetMachine::addInstSelector(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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// Install an instruction selector.
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PM.add(createX86ISelDag(*this, OptLevel));
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// For 32-bit, prepend instructions to set the "global base reg" for PIC.
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if (!Subtarget.is64Bit())
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PM.add(createGlobalBaseRegPass());
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return false;
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}
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bool X86TargetMachine::addPreRegAlloc(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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PM.add(createX86MaxStackAlignmentHeuristicPass());
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return false; // -print-machineinstr shouldn't print after this.
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}
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bool X86TargetMachine::addPostRegAlloc(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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PM.add(createX86FloatingPointStackifierPass());
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return true; // -print-machineinstr should print after this.
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}
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bool X86TargetMachine::addPreEmitPass(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel) {
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bool ShouldPrint = false;
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if (OptLevel != CodeGenOpt::None &&
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(Subtarget.hasSSE2() || Subtarget.hasAVX())) {
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PM.add(createSSEDomainFixPass());
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ShouldPrint = true;
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}
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if (Subtarget.hasAVX() && UseVZeroUpper) {
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PM.add(createX86IssueVZeroUpperPass());
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ShouldPrint = true;
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}
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return ShouldPrint;
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}
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bool X86TargetMachine::addCodeEmitter(PassManagerBase &PM,
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CodeGenOpt::Level OptLevel,
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JITCodeEmitter &JCE) {
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PM.add(createX86JITCodeEmitterPass(*this, JCE));
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return false;
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}
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