llvm-6502/lib/Target/Sparc
Jakob Stoklund Olesen 31867660cb Add a CoveredBySubRegs property to Register descriptions.
When set, this bit indicates that a register is completely defined by
the value of its sub-registers.

Use the CoveredBySubRegs property to infer which super-registers are
call-preserved given a list of callee-saved registers.  For example, the
ARM registers D8-D15 are callee-saved.  This now automatically implies
that Q4-Q7 are call-preserved.

Conversely, Win64 callees save XMM6-XMM15, but the corresponding
YMM6-YMM15 registers are not call-preserved because they are not fully
defined by their sub-registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148363 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18 00:16:39 +00:00
..
MCTargetDesc Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch 2011-12-20 02:50:00 +00:00
TargetInfo LLVMBuild: Remove trailing newline, which irked me. 2011-12-12 19:48:00 +00:00
CMakeLists.txt Fix up the CMake build for the new files added in r146960, they're 2011-12-20 08:42:11 +00:00
DelaySlotFiller.cpp Add bundle aware API for querying instruction properties and switch the code 2011-12-07 07:15:52 +00:00
FPMover.cpp
LLVMBuild.txt LLVMBuild: Introduce a common section which currently has a list of the 2011-12-12 22:45:54 +00:00
Makefile
README.txt
Sparc.h Fix some leftover control reaches end of non-void function warnings. 2012-01-10 20:47:20 +00:00
Sparc.td
SparcAsmPrinter.cpp Sparc: Implement emitFrameIndexDebugValue and getDebugValue Location hooks. 2011-12-25 18:50:24 +00:00
SparcCallingConv.td
SparcFrameLowering.cpp
SparcFrameLowering.h
SparcInstrFormats.td
SparcInstrInfo.cpp Fix some leftover control reaches end of non-void function warnings. 2012-01-10 20:47:20 +00:00
SparcInstrInfo.h Sparc: Implement emitFrameIndexDebugValue and getDebugValue Location hooks. 2011-12-25 18:50:24 +00:00
SparcInstrInfo.td
SparcISelDAGToDAG.cpp
SparcISelLowering.cpp Remove VectorExtras. This unused helper was written for a type of API that is discouraged now. 2012-01-07 19:42:13 +00:00
SparcISelLowering.h
SparcMachineFunctionInfo.cpp Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch 2011-12-20 02:50:00 +00:00
SparcMachineFunctionInfo.h Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch 2011-12-20 02:50:00 +00:00
SparcRegisterInfo.cpp
SparcRegisterInfo.h
SparcRegisterInfo.td Add a CoveredBySubRegs property to Register descriptions. 2012-01-18 00:16:39 +00:00
SparcSelectionDAGInfo.cpp
SparcSelectionDAGInfo.h
SparcSubtarget.cpp Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch 2011-12-20 02:50:00 +00:00
SparcSubtarget.h Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch 2011-12-20 02:50:00 +00:00
SparcTargetMachine.cpp Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch 2011-12-20 02:50:00 +00:00
SparcTargetMachine.h Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch 2011-12-20 02:50:00 +00:00

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots

* Implement JIT support