Sanjoy Das 319c91bbb0 [TargetInstrInfo] Rename getLdStBaseRegImmOfs and implement for x86. ...

Summary:

TargetInstrInfo::getLdStBaseRegImmOfs to
TargetInstrInfo::getMemOpBaseRegImmOfs and implement for x86.  The
implementation only handles a few easy cases now and will be made more
sophisticated in the future.

This is NFCI: the only user of `getLdStBaseRegImmOfs` (now
`getmemOpBaseRegImmOfs`) is `LoadClusterMotion` and `LoadClusterMotion`
is disabled for x86.

Reviewers: reames, ab, MatzeB, atrick

Reviewed By: MatzeB, atrick

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10199

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239741 91177308-0d34-0410-b5e6-96231b3b80d8

2015-06-15 18:44:14 +00:00

..

AsmParser

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Disassembler

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InstPrinter

Remove unnecessary conversion from StringRef to std::string and back to StringRef. NFC.

2015-06-10 02:07:37 +00:00

MCTargetDesc

AArch64: map bare-metal arm64-macho triple to MachO MC layer.

2015-06-12 23:37:11 +00:00

TargetInfo

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Utils

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AArch64.h

[AArch64] Revert r239711 again. We need to discuss how to share code between AArch64 and ARM backend.

2015-06-15 01:56:40 +00:00

AArch64.td

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AArch64A53Fix835769.cpp

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AArch64A57FPLoadBalancing.cpp

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AArch64AddressTypePromotion.cpp

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AArch64AdvSIMDScalarPass.cpp

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AArch64AsmPrinter.cpp

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AArch64BranchRelaxation.cpp

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AArch64CallingConvention.h

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AArch64CallingConvention.td

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AArch64CleanupLocalDynamicTLSPass.cpp

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AArch64CollectLOH.cpp

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AArch64ConditionalCompares.cpp

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AArch64ConditionOptimizer.cpp

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AArch64DeadRegisterDefinitionsPass.cpp

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AArch64ExpandPseudoInsts.cpp

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AArch64FastISel.cpp

On behalf of Alexandros Lamprineas:

2015-06-15 15:48:44 +00:00

AArch64FrameLowering.cpp

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AArch64FrameLowering.h

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AArch64InstrAtomics.td

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AArch64InstrFormats.td

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AArch64InstrInfo.cpp

[TargetInstrInfo] Rename getLdStBaseRegImmOfs and implement for x86.

2015-06-15 18:44:14 +00:00

AArch64InstrInfo.h

[TargetInstrInfo] Rename getLdStBaseRegImmOfs and implement for x86.

2015-06-15 18:44:14 +00:00

AArch64InstrInfo.td

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AArch64ISelDAGToDAG.cpp

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AArch64ISelLowering.cpp

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AArch64ISelLowering.h

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AArch64LoadStoreOptimizer.cpp

[AArch64] Remove an overly conservative check when generating store pairs.

2015-06-09 20:59:41 +00:00

AArch64MachineCombinerPattern.h

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AArch64MachineFunctionInfo.h

Canonicalize header guards into a common format.

2014-08-13 16:26:38 +00:00

AArch64MCInstLower.cpp

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AArch64MCInstLower.h

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AArch64PBQPRegAlloc.cpp

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AArch64PBQPRegAlloc.h

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AArch64PerfectShuffle.h

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AArch64PromoteConstant.cpp

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AArch64RegisterInfo.cpp

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AArch64RegisterInfo.h

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AArch64RegisterInfo.td

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AArch64SchedA53.td

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AArch64SchedA57.td

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AArch64SchedA57WriteRes.td

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AArch64SchedCyclone.td

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AArch64Schedule.td

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AArch64SelectionDAGInfo.cpp

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AArch64SelectionDAGInfo.h

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AArch64StorePairSuppress.cpp

[TargetInstrInfo] Rename getLdStBaseRegImmOfs and implement for x86.

2015-06-15 18:44:14 +00:00

AArch64Subtarget.cpp

Replace string GNU Triples with llvm::Triple in MCSubtargetInfo and create*MCSubtargetInfo(). NFC.

2015-06-10 12:11:26 +00:00

AArch64Subtarget.h

Rename TargetSubtargetInfo::enablePostMachineScheduler() to enablePostRAScheduler()

2015-06-13 03:42:16 +00:00

AArch64TargetMachine.cpp

[AArch64] Revert r239711 again. We need to discuss how to share code between AArch64 and ARM backend.

2015-06-15 01:56:40 +00:00

AArch64TargetMachine.h

Replace string GNU Triples with llvm::Triple in TargetMachine. NFC.

2015-06-11 19:41:26 +00:00

AArch64TargetObjectFile.cpp

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AArch64TargetObjectFile.h

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AArch64TargetTransformInfo.cpp

[AArch64] Revert r239711 again. We need to discuss how to share code between AArch64 and ARM backend.

2015-06-15 01:56:40 +00:00

AArch64TargetTransformInfo.h

[AArch64] Revert r239711 again. We need to discuss how to share code between AArch64 and ARM backend.

2015-06-15 01:56:40 +00:00

CMakeLists.txt

[AArch64] Revert r239711 again. We need to discuss how to share code between AArch64 and ARM backend.

2015-06-15 01:56:40 +00:00

LLVMBuild.txt

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Makefile

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