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https://github.com/c64scene-ar/llvm-6502.git
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319dfa3fb3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97673 91177308-0d34-0410-b5e6-96231b3b80d8
246 lines
8.1 KiB
C++
246 lines
8.1 KiB
C++
//===-- MachineCSE.cpp - Machine Common Subexpression Elimination Pass ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass performs global common subexpression elimination on machine
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// instructions using a scoped hash table based value numbering scheme. It
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// must be run while the machine function is still in SSA form.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "machine-cse"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/ADT/ScopedHashTable.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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STATISTIC(NumCoalesces, "Number of copies coalesced");
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STATISTIC(NumCSEs, "Number of common subexpression eliminated");
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namespace llvm {
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template<> struct DenseMapInfo<MachineInstr*> {
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static inline MachineInstr *getEmptyKey() {
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return 0;
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}
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static inline MachineInstr *getTombstoneKey() {
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return reinterpret_cast<MachineInstr*>(-1);
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}
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static unsigned getHashValue(const MachineInstr* const &MI) {
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unsigned Hash = MI->getOpcode() * 37;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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uint64_t Key = (uint64_t)MO.getType() << 32;
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switch (MO.getType()) {
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default: break;
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case MachineOperand::MO_Register:
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if (MO.isDef() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
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continue; // Skip virtual register defs.
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Key |= MO.getReg();
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break;
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case MachineOperand::MO_Immediate:
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Key |= MO.getImm();
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break;
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case MachineOperand::MO_FrameIndex:
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case MachineOperand::MO_ConstantPoolIndex:
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case MachineOperand::MO_JumpTableIndex:
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Key |= MO.getIndex();
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break;
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case MachineOperand::MO_MachineBasicBlock:
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Key |= DenseMapInfo<void*>::getHashValue(MO.getMBB());
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break;
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case MachineOperand::MO_GlobalAddress:
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Key |= DenseMapInfo<void*>::getHashValue(MO.getGlobal());
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break;
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case MachineOperand::MO_BlockAddress:
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Key |= DenseMapInfo<void*>::getHashValue(MO.getBlockAddress());
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break;
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}
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Key += ~(Key << 32);
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Key ^= (Key >> 22);
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Key += ~(Key << 13);
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Key ^= (Key >> 8);
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Key += (Key << 3);
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Key ^= (Key >> 15);
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Key += ~(Key << 27);
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Key ^= (Key >> 31);
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Hash = (unsigned)Key + Hash * 37;
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}
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return Hash;
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}
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static bool isEqual(const MachineInstr* const &LHS,
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const MachineInstr* const &RHS) {
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if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
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LHS == getEmptyKey() || LHS == getTombstoneKey())
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return LHS == RHS;
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return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
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}
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};
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} // end llvm namespace
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namespace {
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class MachineCSE : public MachineFunctionPass {
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const TargetInstrInfo *TII;
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MachineRegisterInfo *MRI;
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MachineDominatorTree *DT;
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public:
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static char ID; // Pass identification
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MachineCSE() : MachineFunctionPass(&ID), CurrVN(0) {}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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}
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private:
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unsigned CurrVN;
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ScopedHashTable<MachineInstr*, unsigned> VNT;
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SmallVector<MachineInstr*, 64> Exps;
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bool PerformTrivialCoalescing(MachineInstr *MI, MachineBasicBlock *MBB);
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bool ProcessBlock(MachineDomTreeNode *Node);
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};
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} // end anonymous namespace
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char MachineCSE::ID = 0;
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static RegisterPass<MachineCSE>
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X("machine-cse", "Machine Common Subexpression Elimination");
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FunctionPass *llvm::createMachineCSEPass() { return new MachineCSE(); }
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bool MachineCSE::PerformTrivialCoalescing(MachineInstr *MI,
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MachineBasicBlock *MBB) {
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bool Changed = false;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isUse())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg || TargetRegisterInfo::isPhysicalRegister(Reg))
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continue;
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if (!MRI->hasOneUse(Reg))
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// Only coalesce single use copies. This ensure the copy will be
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// deleted.
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continue;
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MachineInstr *DefMI = MRI->getVRegDef(Reg);
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if (DefMI->getParent() != MBB)
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continue;
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unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
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if (TII->isMoveInstr(*DefMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
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TargetRegisterInfo::isVirtualRegister(SrcReg) &&
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!SrcSubIdx && !DstSubIdx) {
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MO.setReg(SrcReg);
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DefMI->eraseFromParent();
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++NumCoalesces;
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Changed = true;
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}
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}
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return Changed;
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}
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static bool hasLivePhysRegDefUse(MachineInstr *MI) {
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg)
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continue;
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// FIXME: This is obviously overly conservative. On x86 lots of instructions
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// will def EFLAGS and they are not marked dead at this point.
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if (TargetRegisterInfo::isPhysicalRegister(Reg) &&
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!(MO.isDef() && MO.isDead()))
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return true;
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}
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return false;
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}
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bool MachineCSE::ProcessBlock(MachineDomTreeNode *Node) {
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bool Changed = false;
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ScopedHashTableScope<MachineInstr*, unsigned> VNTS(VNT);
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MachineBasicBlock *MBB = Node->getBlock();
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for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ) {
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MachineInstr *MI = &*I;
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++I;
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bool SawStore = false;
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if (!MI->isSafeToMove(TII, 0, SawStore))
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continue;
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// Ignore copies or instructions that read / write physical registers
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// (except for dead defs of physical registers).
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unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
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if (TII->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) ||
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MI->isExtractSubreg() || MI->isInsertSubreg() || MI->isSubregToReg())
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continue;
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if (hasLivePhysRegDefUse(MI))
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continue;
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bool FoundCSE = VNT.count(MI);
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if (!FoundCSE) {
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// Look for trivial copy coalescing opportunities.
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if (PerformTrivialCoalescing(MI, MBB))
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FoundCSE = VNT.count(MI);
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}
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if (!FoundCSE) {
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VNT.insert(MI, CurrVN++);
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Exps.push_back(MI);
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continue;
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}
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// Found a common subexpression, eliminate it.
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unsigned CSVN = VNT.lookup(MI);
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MachineInstr *CSMI = Exps[CSVN];
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DEBUG(dbgs() << "Examining: " << *MI);
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DEBUG(dbgs() << "*** Found a common subexpression: " << *CSMI);
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unsigned NumDefs = MI->getDesc().getNumDefs();
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for (unsigned i = 0, e = MI->getNumOperands(); NumDefs && i != e; ++i) {
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MachineOperand &MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isDef())
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continue;
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unsigned OldReg = MO.getReg();
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unsigned NewReg = CSMI->getOperand(i).getReg();
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assert(OldReg != NewReg &&
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TargetRegisterInfo::isVirtualRegister(OldReg) &&
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TargetRegisterInfo::isVirtualRegister(NewReg) &&
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"Do not CSE physical register defs!");
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MRI->replaceRegWith(OldReg, NewReg);
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--NumDefs;
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}
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MI->eraseFromParent();
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++NumCSEs;
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}
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// Recursively call ProcessBlock with childred.
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const std::vector<MachineDomTreeNode*> &Children = Node->getChildren();
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for (unsigned i = 0, e = Children.size(); i != e; ++i)
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Changed |= ProcessBlock(Children[i]);
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return Changed;
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}
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bool MachineCSE::runOnMachineFunction(MachineFunction &MF) {
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TII = MF.getTarget().getInstrInfo();
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MRI = &MF.getRegInfo();
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DT = &getAnalysis<MachineDominatorTree>();
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return ProcessBlock(DT->getRootNode());
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}
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