llvm-6502/test/CodeGen
Dan Gohman 8ce05daf54 Remove the logic for reasoning about NaNs from the code that forms
SSE min and max instructions. The real thing this code needs to be
concerned about is negative zero.

Update the sse-minmax.ll test accordingly, and add tests for
-enable-unsafe-fp-math mode as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96775 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-22 04:03:39 +00:00
..
Alpha
ARM Use NEON vmin/vmax instructions for floating-point selects. 2010-02-18 06:05:53 +00:00
Blackfin
CBackend
CellSPU
CPP
Generic Preliminary patch to improve dwarf EH generation - Hooks to return Personality / FDE / LSDA / TType encoding depending on target / options (e.g. code model / relocation model) - MCIzation of Dwarf EH printer to use encoding information - Stub generation for ELF target (needed for indirect references) - Some other small changes here and there 2010-02-15 22:35:59 +00:00
Mips
MSP430 IT turns out that during jumpless setcc lowering eq and ne were swapped. 2010-02-21 12:28:58 +00:00
PIC16
PowerPC When emitting an instruction which depends on both a post-incremented 2010-02-22 03:59:54 +00:00
SPARC add support for the sparcv9-*-* target triple to turn on 2010-02-04 06:34:01 +00:00
SystemZ
Thumb
Thumb2 Last week we were generating code with duplicate induction variables in this 2010-02-15 21:56:40 +00:00
X86 Remove the logic for reasoning about NaNs from the code that forms 2010-02-22 04:03:39 +00:00
XCore