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https://github.com/c64scene-ar/llvm-6502.git
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4a888086a4
Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10772 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@240839 91177308-0d34-0410-b5e6-96231b3b80d8
61 lines
1.8 KiB
C++
61 lines
1.8 KiB
C++
//===-- AMDGPUBaseInfo.cpp - AMDGPU Base encoding information--------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUBaseInfo.h"
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#include "llvm/MC/SubtargetFeature.h"
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#define GET_SUBTARGETINFO_ENUM
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#include "AMDGPUGenSubtargetInfo.inc"
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#undef GET_SUBTARGETINFO_ENUM
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namespace llvm {
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namespace AMDGPU {
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IsaVersion getIsaVersion(const FeatureBitset &Features) {
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if (Features.test(FeatureISAVersion7_0_0))
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return {7, 0, 0};
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if (Features.test(FeatureISAVersion7_0_1))
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return {7, 0, 1};
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if (Features.test(FeatureISAVersion8_0_0))
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return {8, 0, 0};
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if (Features.test(FeatureISAVersion8_0_1))
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return {8, 0, 1};
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return {0, 0, 0};
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}
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void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
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const FeatureBitset &Features) {
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IsaVersion ISA = getIsaVersion(Features);
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memset(&Header, 0, sizeof(Header));
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Header.amd_kernel_code_version_major = 1;
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Header.amd_kernel_code_version_minor = 0;
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Header.amd_machine_kind = 1; // AMD_MACHINE_KIND_AMDGPU
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Header.amd_machine_version_major = ISA.Major;
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Header.amd_machine_version_minor = ISA.Minor;
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Header.amd_machine_version_stepping = ISA.Stepping;
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Header.kernel_code_entry_byte_offset = sizeof(Header);
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// wavefront_size is specified as a power of 2: 2^6 = 64 threads.
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Header.wavefront_size = 6;
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// These alignment values are specified in powers of two, so alignment =
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// 2^n. The minimum alignment is 2^4 = 16.
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Header.kernarg_segment_alignment = 4;
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Header.group_segment_alignment = 4;
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Header.private_segment_alignment = 4;
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}
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} // End namespace AMDGPU
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} // End namespace llvm
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