mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7517bbc91a
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156568 91177308-0d34-0410-b5e6-96231b3b80d8
337 lines
10 KiB
TableGen
337 lines
10 KiB
TableGen
//==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Hexagon Intruction Flags +
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//
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// *** Must match HexagonBaseInfo.h ***
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//===----------------------------------------------------------------------===//
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class Type<bits<5> t> {
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bits<5> Value = t;
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}
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def TypePSEUDO : Type<0>;
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def TypeALU32 : Type<1>;
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def TypeCR : Type<2>;
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def TypeJR : Type<3>;
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def TypeJ : Type<4>;
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def TypeLD : Type<5>;
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def TypeST : Type<6>;
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def TypeSYSTEM : Type<7>;
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def TypeXTYPE : Type<8>;
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def TypeMARKER : Type<31>;
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//===----------------------------------------------------------------------===//
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// Intruction Class Declaration +
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//===----------------------------------------------------------------------===//
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class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
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string cstr, InstrItinClass itin, Type type> : Instruction {
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field bits<32> Inst;
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let Namespace = "Hexagon";
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let AsmString = asmstr;
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let Pattern = pattern;
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let Constraints = cstr;
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let Itinerary = itin;
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let Size = 4;
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// *** Must match HexagonBaseInfo.h ***
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// Instruction type according to the ISA.
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Type HexagonType = type;
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let TSFlags{4-0} = HexagonType.Value;
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// Solo instructions, i.e., those that cannot be in a packet with others.
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bits<1> isHexagonSolo = 0;
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let TSFlags{5} = isHexagonSolo;
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// Predicated instructions.
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bits<1> isPredicated = 0;
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let TSFlags{6} = isPredicated;
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// *** The code above must match HexagonBaseInfo.h ***
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}
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//===----------------------------------------------------------------------===//
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// Intruction Classes Definitions +
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//===----------------------------------------------------------------------===//
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// LD Instruction Class in V2/V3/V4.
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// Definition of the instruction class NOT CHANGED.
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class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", LD, TypeLD> {
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bits<5> rd;
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bits<5> rs;
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bits<13> imm13;
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}
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class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", LD, TypeLD> {
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bits<5> rd;
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bits<5> rs;
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bits<13> imm13;
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let mayLoad = 1;
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}
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// LD Instruction Class in V2/V3/V4.
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// Definition of the instruction class NOT CHANGED.
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class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern,
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string cstr>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, LD, TypeLD> {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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bits<13> imm13;
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}
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// ST Instruction Class in V2/V3 can take SLOT0 only.
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// ST Instruction Class in V4 can take SLOT0 & SLOT1.
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// Definition of the instruction class CHANGED from V2/V3 to V4.
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class STInst<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", ST, TypeST> {
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bits<5> rd;
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bits<5> rs;
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bits<13> imm13;
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}
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class STInst2<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", ST, TypeST> {
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bits<5> rd;
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bits<5> rs;
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bits<13> imm13;
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let mayStore = 1;
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}
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// SYSTEM Instruction Class in V4 can take SLOT0 only
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// In V2/V3 we used ST for this but in v4 ST can take SLOT0 or SLOT1.
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class SYSInst<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", SYS, TypeSYSTEM> {
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bits<5> rd;
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bits<5> rs;
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bits<13> imm13;
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}
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// ST Instruction Class in V2/V3 can take SLOT0 only.
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// ST Instruction Class in V4 can take SLOT0 & SLOT1.
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// Definition of the instruction class CHANGED from V2/V3 to V4.
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class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern,
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string cstr>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, ST, TypeST> {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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bits<13> imm13;
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}
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// ALU32 Instruction Class in V2/V3/V4.
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// Definition of the instruction class NOT CHANGED.
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class ALU32Type<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", ALU32, TypeALU32> {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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bits<16> imm16;
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bits<16> imm16_2;
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}
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// ALU64 Instruction Class in V2/V3.
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// XTYPE Instruction Class in V4.
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// Definition of the instruction class NOT CHANGED.
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// Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4.
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class ALU64Type<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", ALU64, TypeXTYPE> {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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bits<16> imm16;
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bits<16> imm16_2;
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}
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class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
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string cstr>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, ALU64, TypeXTYPE> {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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bits<16> imm16;
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bits<16> imm16_2;
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}
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// M Instruction Class in V2/V3.
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// XTYPE Instruction Class in V4.
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// Definition of the instruction class NOT CHANGED.
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// Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
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class MInst<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", M, TypeXTYPE> {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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}
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// M Instruction Class in V2/V3.
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// XTYPE Instruction Class in V4.
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// Definition of the instruction class NOT CHANGED.
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// Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
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class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
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string cstr>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, M, TypeXTYPE> {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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}
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// S Instruction Class in V2/V3.
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// XTYPE Instruction Class in V4.
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// Definition of the instruction class NOT CHANGED.
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// Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
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class SInst<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", S, TypeXTYPE> {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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}
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// S Instruction Class in V2/V3.
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// XTYPE Instruction Class in V4.
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// Definition of the instruction class NOT CHANGED.
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// Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
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class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern,
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string cstr>
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: InstHexagon<outs, ins, asmstr, pattern, cstr, S, TypeXTYPE> {
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// : InstHexagon<outs, ins, asmstr, pattern, cstr, S> {
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// : InstHexagon<outs, ins, asmstr, pattern, cstr, !if(V4T, XTYPE_V4, S)> {
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bits<5> rd;
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bits<5> rs;
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bits<5> rt;
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}
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// J Instruction Class in V2/V3/V4.
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// Definition of the instruction class NOT CHANGED.
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class JType<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", J, TypeJ> {
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bits<16> imm16;
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}
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// JR Instruction Class in V2/V3/V4.
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// Definition of the instruction class NOT CHANGED.
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class JRType<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", JR, TypeJR> {
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bits<5> rs;
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bits<5> pu; // Predicate register
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}
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// CR Instruction Class in V2/V3/V4.
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// Definition of the instruction class NOT CHANGED.
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class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", CR, TypeCR> {
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bits<5> rs;
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bits<10> imm10;
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}
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class Marker<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", MARKER, TypeMARKER> {
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let isCodeGenOnly = 1;
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let isPseudo = 1;
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}
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class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstHexagon<outs, ins, asmstr, pattern, "", PSEUDO, TypePSEUDO> {
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let isCodeGenOnly = 1;
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let isPseudo = 1;
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}
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//===----------------------------------------------------------------------===//
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// Intruction Classes Definitions -
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//===----------------------------------------------------------------------===//
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//
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// ALU32 patterns
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//.
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class ALU32_rr<dag outs, dag ins, string asmstr, list<dag> pattern>
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: ALU32Type<outs, ins, asmstr, pattern> {
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}
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class ALU32_ir<dag outs, dag ins, string asmstr, list<dag> pattern>
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: ALU32Type<outs, ins, asmstr, pattern> {
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let rt{0-4} = 0;
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}
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class ALU32_ri<dag outs, dag ins, string asmstr, list<dag> pattern>
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: ALU32Type<outs, ins, asmstr, pattern> {
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let rt{0-4} = 0;
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}
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class ALU32_ii<dag outs, dag ins, string asmstr, list<dag> pattern>
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: ALU32Type<outs, ins, asmstr, pattern> {
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let rt{0-4} = 0;
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}
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//
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// ALU64 patterns.
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//
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class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern>
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: ALU64Type<outs, ins, asmstr, pattern> {
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}
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class ALU64_ri<dag outs, dag ins, string asmstr, list<dag> pattern>
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: ALU64Type<outs, ins, asmstr, pattern> {
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let rt{0-4} = 0;
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}
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// J Type Instructions.
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class JInst<dag outs, dag ins, string asmstr, list<dag> pattern>
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: JType<outs, ins, asmstr, pattern> {
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}
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// JR type Instructions.
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class JRInst<dag outs, dag ins, string asmstr, list<dag> pattern>
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: JRType<outs, ins, asmstr, pattern> {
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}
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// Post increment ST Instruction.
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class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern,
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string cstr>
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: STInstPost<outs, ins, asmstr, pattern, cstr> {
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let rt{0-4} = 0;
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}
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class STInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern,
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string cstr>
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: STInstPost<outs, ins, asmstr, pattern, cstr> {
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let rt{0-4} = 0;
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let mayStore = 1;
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}
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// Post increment LD Instruction.
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class LDInstPI<dag outs, dag ins, string asmstr, list<dag> pattern,
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string cstr>
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: LDInstPost<outs, ins, asmstr, pattern, cstr> {
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let rt{0-4} = 0;
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}
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class LDInst2PI<dag outs, dag ins, string asmstr, list<dag> pattern,
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string cstr>
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: LDInstPost<outs, ins, asmstr, pattern, cstr> {
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let rt{0-4} = 0;
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let mayLoad = 1;
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}
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//===----------------------------------------------------------------------===//
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// V4 Instruction Format Definitions +
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//===----------------------------------------------------------------------===//
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include "HexagonInstrFormatsV4.td"
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//===----------------------------------------------------------------------===//
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// V4 Instruction Format Definitions +
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//===----------------------------------------------------------------------===//
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