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d57cdd5683
- If destination is a physical register and it has a subreg index, use the sub-register instead. This fixes PR5423. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88745 91177308-0d34-0410-b5e6-96231b3b80d8
106 lines
2.9 KiB
C++
106 lines
2.9 KiB
C++
//===- ARMInstrInfo.cpp - ARM Instruction Information -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARM implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMInstrInfo.h"
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#include "ARM.h"
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#include "ARMAddressingModes.h"
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#include "ARMGenInstrInfo.inc"
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#include "ARMMachineFunctionInfo.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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#include "llvm/MC/MCAsmInfo.h"
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using namespace llvm;
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ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
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: ARMBaseInstrInfo(STI), RI(*this, STI) {
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}
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unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const {
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switch (Opc) {
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default: break;
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case ARM::LDR_PRE:
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case ARM::LDR_POST:
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return ARM::LDR;
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case ARM::LDRH_PRE:
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case ARM::LDRH_POST:
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return ARM::LDRH;
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case ARM::LDRB_PRE:
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case ARM::LDRB_POST:
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return ARM::LDRB;
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case ARM::LDRSH_PRE:
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case ARM::LDRSH_POST:
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return ARM::LDRSH;
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case ARM::LDRSB_PRE:
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case ARM::LDRSB_POST:
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return ARM::LDRSB;
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case ARM::STR_PRE:
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case ARM::STR_POST:
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return ARM::STR;
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case ARM::STRH_PRE:
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case ARM::STRH_POST:
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return ARM::STRH;
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case ARM::STRB_PRE:
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case ARM::STRB_POST:
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return ARM::STRB;
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}
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return 0;
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}
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bool ARMInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
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if (MBB.empty()) return false;
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switch (MBB.back().getOpcode()) {
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case ARM::BX_RET: // Return.
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case ARM::LDM_RET:
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case ARM::B:
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case ARM::BRIND:
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case ARM::BR_JTr: // Jumptable branch.
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case ARM::BR_JTm: // Jumptable branch through mem.
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case ARM::BR_JTadd: // Jumptable branch add to pc.
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return true;
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default:
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break;
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}
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return false;
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}
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void ARMInstrInfo::
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reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig,
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const TargetRegisterInfo *TRI) const {
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DebugLoc dl = Orig->getDebugLoc();
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unsigned Opcode = Orig->getOpcode();
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switch (Opcode) {
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default:
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break;
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case ARM::MOVi2pieces: {
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RI.emitLoadConstPool(MBB, I, dl,
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DestReg, SubIdx,
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Orig->getOperand(1).getImm(),
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(ARMCC::CondCodes)Orig->getOperand(2).getImm(),
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Orig->getOperand(3).getReg());
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MachineInstr *NewMI = prior(I);
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NewMI->getOperand(0).setSubReg(SubIdx);
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return;
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}
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}
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return ARMBaseInstrInfo::reMaterialize(MBB, I, DestReg, SubIdx, Orig, TRI);
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}
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