mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 04:30:12 +00:00
ec49b722fd
4i32 shuffles for single insertions into zero vectors lowers to X86vzmovl which was using (v)blendps - causing domain switch stalls. This patch fixes this by using (v)pblendw instead. The updated tests on test/CodeGen/X86/sse41.ll still contain a domain stall due to the use of insertps - I'm looking at fixing this in a future patch. Differential Revision: http://reviews.llvm.org/D6458 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223165 91177308-0d34-0410-b5e6-96231b3b80d8
1203 lines
43 KiB
LLVM
1203 lines
43 KiB
LLVM
; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse4.1 -mcpu=penryn | FileCheck %s --check-prefix=X32
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; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=sse4.1 -mcpu=penryn | FileCheck %s --check-prefix=X64
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@g16 = external global i16
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define <4 x i32> @pinsrd_1(i32 %s, <4 x i32> %tmp) nounwind {
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; X32-LABEL: pinsrd_1:
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; X32: ## BB#0:
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; X32-NEXT: pinsrd $1, {{[0-9]+}}(%esp), %xmm0
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; X32-NEXT: retl
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;
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; X64-LABEL: pinsrd_1:
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; X64: ## BB#0:
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; X64-NEXT: pinsrd $1, %edi, %xmm0
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; X64-NEXT: retq
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%tmp1 = insertelement <4 x i32> %tmp, i32 %s, i32 1
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ret <4 x i32> %tmp1
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}
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define <16 x i8> @pinsrb_1(i8 %s, <16 x i8> %tmp) nounwind {
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; X32-LABEL: pinsrb_1:
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; X32: ## BB#0:
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; X32-NEXT: pinsrb $1, {{[0-9]+}}(%esp), %xmm0
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; X32-NEXT: retl
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;
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; X64-LABEL: pinsrb_1:
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; X64: ## BB#0:
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; X64-NEXT: pinsrb $1, %edi, %xmm0
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; X64-NEXT: retq
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%tmp1 = insertelement <16 x i8> %tmp, i8 %s, i32 1
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ret <16 x i8> %tmp1
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}
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define <2 x i64> @pmovsxbd_1(i32* %p) nounwind {
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; X32-LABEL: pmovsxbd_1:
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; X32: ## BB#0: ## %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: pmovsxbd (%eax), %xmm0
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; X32-NEXT: retl
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;
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; X64-LABEL: pmovsxbd_1:
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; X64: ## BB#0: ## %entry
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; X64-NEXT: pmovsxbd (%rdi), %xmm0
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; X64-NEXT: retq
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entry:
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%0 = load i32* %p, align 4
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%1 = insertelement <4 x i32> undef, i32 %0, i32 0
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%2 = insertelement <4 x i32> %1, i32 0, i32 1
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%3 = insertelement <4 x i32> %2, i32 0, i32 2
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%4 = insertelement <4 x i32> %3, i32 0, i32 3
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%5 = bitcast <4 x i32> %4 to <16 x i8>
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%6 = tail call <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8> %5) nounwind readnone
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%7 = bitcast <4 x i32> %6 to <2 x i64>
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ret <2 x i64> %7
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}
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define <2 x i64> @pmovsxwd_1(i64* %p) nounwind readonly {
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; X32-LABEL: pmovsxwd_1:
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; X32: ## BB#0: ## %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: pmovsxwd (%eax), %xmm0
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; X32-NEXT: retl
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;
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; X64-LABEL: pmovsxwd_1:
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; X64: ## BB#0: ## %entry
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; X64-NEXT: pmovsxwd (%rdi), %xmm0
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; X64-NEXT: retq
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entry:
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%0 = load i64* %p ; <i64> [#uses=1]
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%tmp2 = insertelement <2 x i64> zeroinitializer, i64 %0, i32 0 ; <<2 x i64>> [#uses=1]
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%1 = bitcast <2 x i64> %tmp2 to <8 x i16> ; <<8 x i16>> [#uses=1]
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%2 = tail call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %1) nounwind readnone ; <<4 x i32>> [#uses=1]
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%3 = bitcast <4 x i32> %2 to <2 x i64> ; <<2 x i64>> [#uses=1]
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ret <2 x i64> %3
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}
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define <2 x i64> @pmovzxbq_1() nounwind {
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; X32-LABEL: pmovzxbq_1:
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; X32: ## BB#0: ## %entry
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; X32-NEXT: movl L_g16$non_lazy_ptr, %eax
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; X32-NEXT: pmovzxbq (%eax), %xmm0
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; X32-NEXT: retl
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;
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; X64-LABEL: pmovzxbq_1:
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; X64: ## BB#0: ## %entry
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; X64-NEXT: movq _g16@{{.*}}(%rip), %rax
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; X64-NEXT: pmovzxbq (%rax), %xmm0
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; X64-NEXT: retq
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entry:
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%0 = load i16* @g16, align 2 ; <i16> [#uses=1]
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%1 = insertelement <8 x i16> undef, i16 %0, i32 0 ; <<8 x i16>> [#uses=1]
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%2 = bitcast <8 x i16> %1 to <16 x i8> ; <<16 x i8>> [#uses=1]
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%3 = tail call <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8> %2) nounwind readnone ; <<2 x i64>> [#uses=1]
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ret <2 x i64> %3
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}
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declare <4 x i32> @llvm.x86.sse41.pmovsxbd(<16 x i8>) nounwind readnone
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declare <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16>) nounwind readnone
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declare <2 x i64> @llvm.x86.sse41.pmovzxbq(<16 x i8>) nounwind readnone
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define i32 @extractps_1(<4 x float> %v) nounwind {
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; X32-LABEL: extractps_1:
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; X32: ## BB#0:
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; X32-NEXT: extractps $3, %xmm0, %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: extractps_1:
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; X64: ## BB#0:
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; X64-NEXT: extractps $3, %xmm0, %eax
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; X64-NEXT: retq
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%s = extractelement <4 x float> %v, i32 3
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%i = bitcast float %s to i32
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ret i32 %i
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}
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define i32 @extractps_2(<4 x float> %v) nounwind {
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; X32-LABEL: extractps_2:
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; X32: ## BB#0:
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; X32-NEXT: extractps $3, %xmm0, %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: extractps_2:
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; X64: ## BB#0:
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; X64-NEXT: extractps $3, %xmm0, %eax
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; X64-NEXT: retq
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%t = bitcast <4 x float> %v to <4 x i32>
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%s = extractelement <4 x i32> %t, i32 3
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ret i32 %s
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}
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; The non-store form of extractps puts its result into a GPR.
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; This makes it suitable for an extract from a <4 x float> that
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; is bitcasted to i32, but unsuitable for much of anything else.
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define float @ext_1(<4 x float> %v) nounwind {
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; X32-LABEL: ext_1:
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; X32: ## BB#0:
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; X32-NEXT: pushl %eax
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; X32-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
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; X32-NEXT: addss LCPI7_0, %xmm0
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; X32-NEXT: movss %xmm0, (%esp)
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; X32-NEXT: flds (%esp)
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; X32-NEXT: popl %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: ext_1:
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; X64: ## BB#0:
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; X64-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
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; X64-NEXT: addss {{.*}}(%rip), %xmm0
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; X64-NEXT: retq
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%s = extractelement <4 x float> %v, i32 3
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%t = fadd float %s, 1.0
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ret float %t
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}
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define float @ext_2(<4 x float> %v) nounwind {
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; X32-LABEL: ext_2:
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; X32: ## BB#0:
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; X32-NEXT: pushl %eax
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; X32-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
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; X32-NEXT: movss %xmm0, (%esp)
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; X32-NEXT: flds (%esp)
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; X32-NEXT: popl %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: ext_2:
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; X64: ## BB#0:
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; X64-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,1,2,3]
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; X64-NEXT: retq
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%s = extractelement <4 x float> %v, i32 3
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ret float %s
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}
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define i32 @ext_3(<4 x i32> %v) nounwind {
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; X32-LABEL: ext_3:
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; X32: ## BB#0:
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; X32-NEXT: pextrd $3, %xmm0, %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: ext_3:
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; X64: ## BB#0:
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; X64-NEXT: pextrd $3, %xmm0, %eax
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; X64-NEXT: retq
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%i = extractelement <4 x i32> %v, i32 3
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ret i32 %i
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}
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define <4 x float> @insertps_1(<4 x float> %t1, <4 x float> %t2) nounwind {
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; X32-LABEL: insertps_1:
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; X32: ## BB#0:
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; X32-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[1,2,3]
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; X32-NEXT: retl
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;
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; X64-LABEL: insertps_1:
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; X64: ## BB#0:
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; X64-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[1,2,3]
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; X64-NEXT: retq
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%tmp1 = call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %t1, <4 x float> %t2, i32 1) nounwind readnone
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ret <4 x float> %tmp1
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}
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declare <4 x float> @llvm.x86.sse41.insertps(<4 x float>, <4 x float>, i32) nounwind readnone
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define <4 x float> @insertps_2(<4 x float> %t1, float %t2) nounwind {
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; X32-LABEL: insertps_2:
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; X32: ## BB#0:
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; X32-NEXT: insertps $0, {{[0-9]+}}(%esp), %xmm0
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; X32-NEXT: retl
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;
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; X64-LABEL: insertps_2:
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; X64: ## BB#0:
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; X64-NEXT: insertps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; X64-NEXT: retq
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%tmp1 = insertelement <4 x float> %t1, float %t2, i32 0
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ret <4 x float> %tmp1
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}
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define <4 x float> @insertps_3(<4 x float> %t1, <4 x float> %t2) nounwind {
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; X32-LABEL: insertps_3:
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; X32: ## BB#0:
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; X32-NEXT: insertps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; X32-NEXT: retl
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;
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; X64-LABEL: insertps_3:
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; X64: ## BB#0:
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; X64-NEXT: insertps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
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; X64-NEXT: retq
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%tmp2 = extractelement <4 x float> %t2, i32 0
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%tmp1 = insertelement <4 x float> %t1, float %tmp2, i32 0
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ret <4 x float> %tmp1
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}
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define i32 @ptestz_1(<2 x i64> %t1, <2 x i64> %t2) nounwind {
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; X32-LABEL: ptestz_1:
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; X32: ## BB#0:
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; X32-NEXT: ptest %xmm1, %xmm0
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; X32-NEXT: sete %al
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; X32-NEXT: movzbl %al, %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: ptestz_1:
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; X64: ## BB#0:
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; X64-NEXT: ptest %xmm1, %xmm0
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; X64-NEXT: sete %al
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; X64-NEXT: movzbl %al, %eax
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; X64-NEXT: retq
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%tmp1 = call i32 @llvm.x86.sse41.ptestz(<2 x i64> %t1, <2 x i64> %t2) nounwind readnone
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ret i32 %tmp1
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}
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define i32 @ptestz_2(<2 x i64> %t1, <2 x i64> %t2) nounwind {
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; X32-LABEL: ptestz_2:
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; X32: ## BB#0:
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; X32-NEXT: ptest %xmm1, %xmm0
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; X32-NEXT: sbbl %eax, %eax
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; X32-NEXT: andl $1, %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: ptestz_2:
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; X64: ## BB#0:
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; X64-NEXT: ptest %xmm1, %xmm0
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; X64-NEXT: sbbl %eax, %eax
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; X64-NEXT: andl $1, %eax
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; X64-NEXT: retq
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%tmp1 = call i32 @llvm.x86.sse41.ptestc(<2 x i64> %t1, <2 x i64> %t2) nounwind readnone
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ret i32 %tmp1
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}
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define i32 @ptestz_3(<2 x i64> %t1, <2 x i64> %t2) nounwind {
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; X32-LABEL: ptestz_3:
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; X32: ## BB#0:
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; X32-NEXT: ptest %xmm1, %xmm0
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; X32-NEXT: seta %al
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; X32-NEXT: movzbl %al, %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: ptestz_3:
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; X64: ## BB#0:
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; X64-NEXT: ptest %xmm1, %xmm0
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; X64-NEXT: seta %al
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; X64-NEXT: movzbl %al, %eax
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; X64-NEXT: retq
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%tmp1 = call i32 @llvm.x86.sse41.ptestnzc(<2 x i64> %t1, <2 x i64> %t2) nounwind readnone
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ret i32 %tmp1
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}
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declare i32 @llvm.x86.sse41.ptestz(<2 x i64>, <2 x i64>) nounwind readnone
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declare i32 @llvm.x86.sse41.ptestc(<2 x i64>, <2 x i64>) nounwind readnone
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declare i32 @llvm.x86.sse41.ptestnzc(<2 x i64>, <2 x i64>) nounwind readnone
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; This used to compile to insertps $0 + insertps $16. insertps $0 is always
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; pointless.
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define <2 x float> @buildvector(<2 x float> %A, <2 x float> %B) nounwind {
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; X32-LABEL: buildvector:
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; X32: ## BB#0: ## %entry
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; X32-NEXT: movaps %xmm0, %xmm2
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; X32-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,2,3]
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; X32-NEXT: addss %xmm1, %xmm0
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; X32-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
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; X32-NEXT: addss %xmm2, %xmm1
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; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
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; X32-NEXT: retl
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;
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; X64-LABEL: buildvector:
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; X64: ## BB#0: ## %entry
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; X64-NEXT: movaps %xmm0, %xmm2
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; X64-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1,2,3]
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; X64-NEXT: addss %xmm1, %xmm0
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; X64-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1,2,3]
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; X64-NEXT: addss %xmm2, %xmm1
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; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[2,3]
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; X64-NEXT: retq
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entry:
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%tmp7 = extractelement <2 x float> %A, i32 0
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%tmp5 = extractelement <2 x float> %A, i32 1
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%tmp3 = extractelement <2 x float> %B, i32 0
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%tmp1 = extractelement <2 x float> %B, i32 1
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%add.r = fadd float %tmp7, %tmp3
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%add.i = fadd float %tmp5, %tmp1
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%tmp11 = insertelement <2 x float> undef, float %add.r, i32 0
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%tmp9 = insertelement <2 x float> %tmp11, float %add.i, i32 1
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ret <2 x float> %tmp9
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}
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define <4 x float> @insertps_from_shufflevector_1(<4 x float> %a, <4 x float>* nocapture readonly %pb) {
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; X32-LABEL: insertps_from_shufflevector_1:
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; X32: ## BB#0: ## %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: insertps $48, (%eax), %xmm0
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; X32-NEXT: retl
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;
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; X64-LABEL: insertps_from_shufflevector_1:
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; X64: ## BB#0: ## %entry
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; X64-NEXT: insertps $48, (%rdi), %xmm0
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; X64-NEXT: retq
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entry:
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%0 = load <4 x float>* %pb, align 16
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%vecinit6 = shufflevector <4 x float> %a, <4 x float> %0, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
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ret <4 x float> %vecinit6
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}
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define <4 x float> @insertps_from_shufflevector_2(<4 x float> %a, <4 x float> %b) {
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; X32-LABEL: insertps_from_shufflevector_2:
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; X32: ## BB#0: ## %entry
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; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[1],xmm0[3]
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; X32-NEXT: retl
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;
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; X64-LABEL: insertps_from_shufflevector_2:
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; X64: ## BB#0: ## %entry
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; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[1],xmm0[3]
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; X64-NEXT: retq
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entry:
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%vecinit6 = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 1, i32 5, i32 3>
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ret <4 x float> %vecinit6
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}
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; For loading an i32 from memory into an xmm register we use pinsrd
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; instead of insertps
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define <4 x i32> @pinsrd_from_shufflevector_i32(<4 x i32> %a, <4 x i32>* nocapture readonly %pb) {
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; X32-LABEL: pinsrd_from_shufflevector_i32:
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; X32: ## BB#0: ## %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: insertps $48, (%eax), %xmm0
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; X32-NEXT: retl
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;
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; X64-LABEL: pinsrd_from_shufflevector_i32:
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; X64: ## BB#0: ## %entry
|
|
; X64-NEXT: insertps $48, (%rdi), %xmm0
|
|
; X64-NEXT: retq
|
|
entry:
|
|
%0 = load <4 x i32>* %pb, align 16
|
|
%vecinit6 = shufflevector <4 x i32> %a, <4 x i32> %0, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
|
|
ret <4 x i32> %vecinit6
|
|
}
|
|
|
|
define <4 x i32> @insertps_from_shufflevector_i32_2(<4 x i32> %a, <4 x i32> %b) {
|
|
; X32-LABEL: insertps_from_shufflevector_i32_2:
|
|
; X32: ## BB#0: ## %entry
|
|
; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[3],xmm0[2,3]
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: insertps_from_shufflevector_i32_2:
|
|
; X64: ## BB#0: ## %entry
|
|
; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[3],xmm0[2,3]
|
|
; X64-NEXT: retq
|
|
entry:
|
|
%vecinit6 = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 7, i32 2, i32 3>
|
|
ret <4 x i32> %vecinit6
|
|
}
|
|
|
|
define <4 x float> @insertps_from_load_ins_elt_undef(<4 x float> %a, float* %b) {
|
|
; X32-LABEL: insertps_from_load_ins_elt_undef:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
; X32-NEXT: insertps $16, (%eax), %xmm0
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: insertps_from_load_ins_elt_undef:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: insertps $16, (%rdi), %xmm0
|
|
; X64-NEXT: retq
|
|
%1 = load float* %b, align 4
|
|
%2 = insertelement <4 x float> undef, float %1, i32 0
|
|
%result = shufflevector <4 x float> %a, <4 x float> %2, <4 x i32> <i32 0, i32 4, i32 2, i32 3>
|
|
ret <4 x float> %result
|
|
}
|
|
|
|
; TODO: Like on pinsrd_from_shufflevector_i32, remove this mov instr
|
|
define <4 x i32> @insertps_from_load_ins_elt_undef_i32(<4 x i32> %a, i32* %b) {
|
|
; X32-LABEL: insertps_from_load_ins_elt_undef_i32:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
; X32-NEXT: movd (%eax), %xmm1
|
|
; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: insertps_from_load_ins_elt_undef_i32:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: movd (%rdi), %xmm1
|
|
; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0],xmm0[3]
|
|
; X64-NEXT: retq
|
|
%1 = load i32* %b, align 4
|
|
%2 = insertelement <4 x i32> undef, i32 %1, i32 0
|
|
%result = shufflevector <4 x i32> %a, <4 x i32> %2, <4 x i32> <i32 0, i32 1, i32 4, i32 3>
|
|
ret <4 x i32> %result
|
|
}
|
|
|
|
;;;;;; Shuffles optimizable with a single insertps or blend instruction
|
|
define <4 x float> @shuf_XYZ0(<4 x float> %x, <4 x float> %a) {
|
|
; X32-LABEL: shuf_XYZ0:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: xorps %xmm1, %xmm1
|
|
; X32-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: shuf_XYZ0:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: xorps %xmm1, %xmm1
|
|
; X64-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[3]
|
|
; X64-NEXT: retq
|
|
%vecext = extractelement <4 x float> %x, i32 0
|
|
%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
|
|
%vecext1 = extractelement <4 x float> %x, i32 1
|
|
%vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
|
|
%vecext3 = extractelement <4 x float> %x, i32 2
|
|
%vecinit4 = insertelement <4 x float> %vecinit2, float %vecext3, i32 2
|
|
%vecinit5 = insertelement <4 x float> %vecinit4, float 0.0, i32 3
|
|
ret <4 x float> %vecinit5
|
|
}
|
|
|
|
define <4 x float> @shuf_XY00(<4 x float> %x, <4 x float> %a) {
|
|
; X32-LABEL: shuf_XY00:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: movq %xmm0, %xmm0
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: shuf_XY00:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: movq %xmm0, %xmm0
|
|
; X64-NEXT: retq
|
|
%vecext = extractelement <4 x float> %x, i32 0
|
|
%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
|
|
%vecext1 = extractelement <4 x float> %x, i32 1
|
|
%vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
|
|
%vecinit3 = insertelement <4 x float> %vecinit2, float 0.0, i32 2
|
|
%vecinit4 = insertelement <4 x float> %vecinit3, float 0.0, i32 3
|
|
ret <4 x float> %vecinit4
|
|
}
|
|
|
|
define <4 x float> @shuf_XYY0(<4 x float> %x, <4 x float> %a) {
|
|
; X32-LABEL: shuf_XYY0:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,1],zero
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: shuf_XYY0:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,1],zero
|
|
; X64-NEXT: retq
|
|
%vecext = extractelement <4 x float> %x, i32 0
|
|
%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
|
|
%vecext1 = extractelement <4 x float> %x, i32 1
|
|
%vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
|
|
%vecinit4 = insertelement <4 x float> %vecinit2, float %vecext1, i32 2
|
|
%vecinit5 = insertelement <4 x float> %vecinit4, float 0.0, i32 3
|
|
ret <4 x float> %vecinit5
|
|
}
|
|
|
|
define <4 x float> @shuf_XYW0(<4 x float> %x, <4 x float> %a) {
|
|
; X32-LABEL: shuf_XYW0:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,3],zero
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: shuf_XYW0:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,3],zero
|
|
; X64-NEXT: retq
|
|
%vecext = extractelement <4 x float> %x, i32 0
|
|
%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
|
|
%vecext1 = extractelement <4 x float> %x, i32 1
|
|
%vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
|
|
%vecext2 = extractelement <4 x float> %x, i32 3
|
|
%vecinit3 = insertelement <4 x float> %vecinit2, float %vecext2, i32 2
|
|
%vecinit4 = insertelement <4 x float> %vecinit3, float 0.0, i32 3
|
|
ret <4 x float> %vecinit4
|
|
}
|
|
|
|
define <4 x float> @shuf_W00W(<4 x float> %x, <4 x float> %a) {
|
|
; X32-LABEL: shuf_W00W:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[3],zero,zero,xmm0[3]
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: shuf_W00W:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[3],zero,zero,xmm0[3]
|
|
; X64-NEXT: retq
|
|
%vecext = extractelement <4 x float> %x, i32 3
|
|
%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
|
|
%vecinit2 = insertelement <4 x float> %vecinit, float 0.0, i32 1
|
|
%vecinit3 = insertelement <4 x float> %vecinit2, float 0.0, i32 2
|
|
%vecinit4 = insertelement <4 x float> %vecinit3, float %vecext, i32 3
|
|
ret <4 x float> %vecinit4
|
|
}
|
|
|
|
define <4 x float> @shuf_X00A(<4 x float> %x, <4 x float> %a) {
|
|
; X32-LABEL: shuf_X00A:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: xorps %xmm2, %xmm2
|
|
; X32-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm2[1,2,3]
|
|
; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: shuf_X00A:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: xorps %xmm2, %xmm2
|
|
; X64-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm2[1,2,3]
|
|
; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
|
|
; X64-NEXT: retq
|
|
%vecext = extractelement <4 x float> %x, i32 0
|
|
%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
|
|
%vecinit1 = insertelement <4 x float> %vecinit, float 0.0, i32 1
|
|
%vecinit2 = insertelement <4 x float> %vecinit1, float 0.0, i32 2
|
|
%vecinit4 = shufflevector <4 x float> %vecinit2, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
|
|
ret <4 x float> %vecinit4
|
|
}
|
|
|
|
define <4 x float> @shuf_X00X(<4 x float> %x, <4 x float> %a) {
|
|
; X32-LABEL: shuf_X00X:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: xorps %xmm1, %xmm1
|
|
; X32-NEXT: blendps {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
|
|
; X32-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm0[0]
|
|
; X32-NEXT: movaps %xmm1, %xmm0
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: shuf_X00X:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: xorps %xmm1, %xmm1
|
|
; X64-NEXT: blendps {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]
|
|
; X64-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm0[0]
|
|
; X64-NEXT: movaps %xmm1, %xmm0
|
|
; X64-NEXT: retq
|
|
%vecext = extractelement <4 x float> %x, i32 0
|
|
%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
|
|
%vecinit1 = insertelement <4 x float> %vecinit, float 0.0, i32 1
|
|
%vecinit2 = insertelement <4 x float> %vecinit1, float 0.0, i32 2
|
|
%vecinit4 = shufflevector <4 x float> %vecinit2, <4 x float> %x, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
|
|
ret <4 x float> %vecinit4
|
|
}
|
|
|
|
define <4 x float> @shuf_X0YC(<4 x float> %x, <4 x float> %a) {
|
|
; X32-LABEL: shuf_X0YC:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: xorps %xmm2, %xmm2
|
|
; X32-NEXT: blendps {{.*#+}} xmm2 = xmm0[0],xmm2[1],xmm0[2,3]
|
|
; X32-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1],xmm0[1],zero
|
|
; X32-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm1[2]
|
|
; X32-NEXT: movaps %xmm2, %xmm0
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: shuf_X0YC:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: xorps %xmm2, %xmm2
|
|
; X64-NEXT: blendps {{.*#+}} xmm2 = xmm0[0],xmm2[1],xmm0[2,3]
|
|
; X64-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1],xmm0[1],zero
|
|
; X64-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm1[2]
|
|
; X64-NEXT: movaps %xmm2, %xmm0
|
|
; X64-NEXT: retq
|
|
%vecext = extractelement <4 x float> %x, i32 0
|
|
%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
|
|
%vecinit1 = insertelement <4 x float> %vecinit, float 0.0, i32 1
|
|
%vecinit3 = shufflevector <4 x float> %vecinit1, <4 x float> %x, <4 x i32> <i32 0, i32 1, i32 5, i32 undef>
|
|
%vecinit5 = shufflevector <4 x float> %vecinit3, <4 x float> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
|
|
ret <4 x float> %vecinit5
|
|
}
|
|
|
|
define <4 x i32> @i32_shuf_XYZ0(<4 x i32> %x, <4 x i32> %a) {
|
|
; X32-LABEL: i32_shuf_XYZ0:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: pxor %xmm1, %xmm1
|
|
; X32-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: i32_shuf_XYZ0:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: pxor %xmm1, %xmm1
|
|
; X64-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
|
|
; X64-NEXT: retq
|
|
%vecext = extractelement <4 x i32> %x, i32 0
|
|
%vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
|
|
%vecext1 = extractelement <4 x i32> %x, i32 1
|
|
%vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 1
|
|
%vecext3 = extractelement <4 x i32> %x, i32 2
|
|
%vecinit4 = insertelement <4 x i32> %vecinit2, i32 %vecext3, i32 2
|
|
%vecinit5 = insertelement <4 x i32> %vecinit4, i32 0, i32 3
|
|
ret <4 x i32> %vecinit5
|
|
}
|
|
|
|
define <4 x i32> @i32_shuf_XY00(<4 x i32> %x, <4 x i32> %a) {
|
|
; X32-LABEL: i32_shuf_XY00:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: movq %xmm0, %xmm0
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: i32_shuf_XY00:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: movq %xmm0, %xmm0
|
|
; X64-NEXT: retq
|
|
%vecext = extractelement <4 x i32> %x, i32 0
|
|
%vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
|
|
%vecext1 = extractelement <4 x i32> %x, i32 1
|
|
%vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 1
|
|
%vecinit3 = insertelement <4 x i32> %vecinit2, i32 0, i32 2
|
|
%vecinit4 = insertelement <4 x i32> %vecinit3, i32 0, i32 3
|
|
ret <4 x i32> %vecinit4
|
|
}
|
|
|
|
define <4 x i32> @i32_shuf_XYY0(<4 x i32> %x, <4 x i32> %a) {
|
|
; X32-LABEL: i32_shuf_XYY0:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,1],zero
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: i32_shuf_XYY0:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,1],zero
|
|
; X64-NEXT: retq
|
|
%vecext = extractelement <4 x i32> %x, i32 0
|
|
%vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
|
|
%vecext1 = extractelement <4 x i32> %x, i32 1
|
|
%vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 1
|
|
%vecinit4 = insertelement <4 x i32> %vecinit2, i32 %vecext1, i32 2
|
|
%vecinit5 = insertelement <4 x i32> %vecinit4, i32 0, i32 3
|
|
ret <4 x i32> %vecinit5
|
|
}
|
|
|
|
define <4 x i32> @i32_shuf_XYW0(<4 x i32> %x, <4 x i32> %a) {
|
|
; X32-LABEL: i32_shuf_XYW0:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,3],zero
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: i32_shuf_XYW0:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,3],zero
|
|
; X64-NEXT: retq
|
|
%vecext = extractelement <4 x i32> %x, i32 0
|
|
%vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
|
|
%vecext1 = extractelement <4 x i32> %x, i32 1
|
|
%vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 1
|
|
%vecext2 = extractelement <4 x i32> %x, i32 3
|
|
%vecinit3 = insertelement <4 x i32> %vecinit2, i32 %vecext2, i32 2
|
|
%vecinit4 = insertelement <4 x i32> %vecinit3, i32 0, i32 3
|
|
ret <4 x i32> %vecinit4
|
|
}
|
|
|
|
define <4 x i32> @i32_shuf_W00W(<4 x i32> %x, <4 x i32> %a) {
|
|
; X32-LABEL: i32_shuf_W00W:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[3],zero,zero,xmm0[3]
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: i32_shuf_W00W:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[3],zero,zero,xmm0[3]
|
|
; X64-NEXT: retq
|
|
%vecext = extractelement <4 x i32> %x, i32 3
|
|
%vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
|
|
%vecinit2 = insertelement <4 x i32> %vecinit, i32 0, i32 1
|
|
%vecinit3 = insertelement <4 x i32> %vecinit2, i32 0, i32 2
|
|
%vecinit4 = insertelement <4 x i32> %vecinit3, i32 %vecext, i32 3
|
|
ret <4 x i32> %vecinit4
|
|
}
|
|
|
|
define <4 x i32> @i32_shuf_X00A(<4 x i32> %x, <4 x i32> %a) {
|
|
; X32-LABEL: i32_shuf_X00A:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: pxor %xmm2, %xmm2
|
|
; X32-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3,4,5,6,7]
|
|
; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: i32_shuf_X00A:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: pxor %xmm2, %xmm2
|
|
; X64-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3,4,5,6,7]
|
|
; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
|
|
; X64-NEXT: retq
|
|
%vecext = extractelement <4 x i32> %x, i32 0
|
|
%vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
|
|
%vecinit1 = insertelement <4 x i32> %vecinit, i32 0, i32 1
|
|
%vecinit2 = insertelement <4 x i32> %vecinit1, i32 0, i32 2
|
|
%vecinit4 = shufflevector <4 x i32> %vecinit2, <4 x i32> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
|
|
ret <4 x i32> %vecinit4
|
|
}
|
|
|
|
define <4 x i32> @i32_shuf_X00X(<4 x i32> %x, <4 x i32> %a) {
|
|
; X32-LABEL: i32_shuf_X00X:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: pxor %xmm1, %xmm1
|
|
; X32-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3,4,5,6,7]
|
|
; X32-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm0[0]
|
|
; X32-NEXT: movaps %xmm1, %xmm0
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: i32_shuf_X00X:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: pxor %xmm1, %xmm1
|
|
; X64-NEXT: pblendw {{.*#+}} xmm1 = xmm0[0,1],xmm1[2,3,4,5,6,7]
|
|
; X64-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm0[0]
|
|
; X64-NEXT: movaps %xmm1, %xmm0
|
|
; X64-NEXT: retq
|
|
%vecext = extractelement <4 x i32> %x, i32 0
|
|
%vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
|
|
%vecinit1 = insertelement <4 x i32> %vecinit, i32 0, i32 1
|
|
%vecinit2 = insertelement <4 x i32> %vecinit1, i32 0, i32 2
|
|
%vecinit4 = shufflevector <4 x i32> %vecinit2, <4 x i32> %x, <4 x i32> <i32 0, i32 1, i32 2, i32 4>
|
|
ret <4 x i32> %vecinit4
|
|
}
|
|
|
|
define <4 x i32> @i32_shuf_X0YC(<4 x i32> %x, <4 x i32> %a) {
|
|
; X32-LABEL: i32_shuf_X0YC:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: pmovzxdq %xmm0, %xmm2
|
|
; X32-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1],xmm0[1],zero
|
|
; X32-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm1[2]
|
|
; X32-NEXT: movaps %xmm2, %xmm0
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: i32_shuf_X0YC:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: pmovzxdq %xmm0, %xmm2
|
|
; X64-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1],xmm0[1],zero
|
|
; X64-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm1[2]
|
|
; X64-NEXT: movaps %xmm2, %xmm0
|
|
; X64-NEXT: retq
|
|
%vecext = extractelement <4 x i32> %x, i32 0
|
|
%vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
|
|
%vecinit1 = insertelement <4 x i32> %vecinit, i32 0, i32 1
|
|
%vecinit3 = shufflevector <4 x i32> %vecinit1, <4 x i32> %x, <4 x i32> <i32 0, i32 1, i32 5, i32 undef>
|
|
%vecinit5 = shufflevector <4 x i32> %vecinit3, <4 x i32> %a, <4 x i32> <i32 0, i32 1, i32 2, i32 6>
|
|
ret <4 x i32> %vecinit5
|
|
}
|
|
|
|
;; Test for a bug in the first implementation of LowerBuildVectorv4x32
|
|
define < 4 x float> @test_insertps_no_undef(<4 x float> %x) {
|
|
; X32-LABEL: test_insertps_no_undef:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: xorps %xmm1, %xmm1
|
|
; X32-NEXT: blendps {{.*#+}} xmm1 = xmm0[0,1,2],xmm1[3]
|
|
; X32-NEXT: maxps %xmm1, %xmm0
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: test_insertps_no_undef:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: xorps %xmm1, %xmm1
|
|
; X64-NEXT: blendps {{.*#+}} xmm1 = xmm0[0,1,2],xmm1[3]
|
|
; X64-NEXT: maxps %xmm1, %xmm0
|
|
; X64-NEXT: retq
|
|
%vecext = extractelement <4 x float> %x, i32 0
|
|
%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
|
|
%vecext1 = extractelement <4 x float> %x, i32 1
|
|
%vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
|
|
%vecext3 = extractelement <4 x float> %x, i32 2
|
|
%vecinit4 = insertelement <4 x float> %vecinit2, float %vecext3, i32 2
|
|
%vecinit5 = insertelement <4 x float> %vecinit4, float 0.0, i32 3
|
|
%mask = fcmp olt <4 x float> %vecinit5, %x
|
|
%res = select <4 x i1> %mask, <4 x float> %x, <4 x float>%vecinit5
|
|
ret <4 x float> %res
|
|
}
|
|
|
|
define <8 x i16> @blendvb_fallback(<8 x i1> %mask, <8 x i16> %x, <8 x i16> %y) {
|
|
; X32-LABEL: blendvb_fallback:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: psllw $15, %xmm0
|
|
; X32-NEXT: psraw $15, %xmm0
|
|
; X32-NEXT: pblendvb %xmm1, %xmm2
|
|
; X32-NEXT: movdqa %xmm2, %xmm0
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: blendvb_fallback:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: psllw $15, %xmm0
|
|
; X64-NEXT: psraw $15, %xmm0
|
|
; X64-NEXT: pblendvb %xmm1, %xmm2
|
|
; X64-NEXT: movdqa %xmm2, %xmm0
|
|
; X64-NEXT: retq
|
|
%ret = select <8 x i1> %mask, <8 x i16> %x, <8 x i16> %y
|
|
ret <8 x i16> %ret
|
|
}
|
|
|
|
; On X32, account for the argument's move to registers
|
|
define <4 x float> @insertps_from_vector_load(<4 x float> %a, <4 x float>* nocapture readonly %pb) {
|
|
; X32-LABEL: insertps_from_vector_load:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
; X32-NEXT: insertps $48, (%eax), %xmm0
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: insertps_from_vector_load:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: insertps $48, (%rdi), %xmm0
|
|
; X64-NEXT: retq
|
|
%1 = load <4 x float>* %pb, align 16
|
|
%2 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %1, i32 48)
|
|
ret <4 x float> %2
|
|
}
|
|
|
|
;; Use a non-zero CountS for insertps
|
|
;; Try to match a bit more of the instr, since we need the load's offset.
|
|
define <4 x float> @insertps_from_vector_load_offset(<4 x float> %a, <4 x float>* nocapture readonly %pb) {
|
|
; X32-LABEL: insertps_from_vector_load_offset:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
; X32-NEXT: insertps $96, 4(%eax), %xmm0
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: insertps_from_vector_load_offset:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: insertps $96, 4(%rdi), %xmm0
|
|
; X64-NEXT: retq
|
|
%1 = load <4 x float>* %pb, align 16
|
|
%2 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %1, i32 96)
|
|
ret <4 x float> %2
|
|
}
|
|
|
|
;; Try to match a bit more of the instr, since we need the load's offset.
|
|
define <4 x float> @insertps_from_vector_load_offset_2(<4 x float> %a, <4 x float>* nocapture readonly %pb, i64 %index) {
|
|
; X32-LABEL: insertps_from_vector_load_offset_2:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
|
; X32-NEXT: shll $4, %ecx
|
|
; X32-NEXT: insertps $-64, 12(%eax,%ecx), %xmm0
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: insertps_from_vector_load_offset_2:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: shlq $4, %rsi
|
|
; X64-NEXT: insertps $-64, 12(%rdi,%rsi), %xmm0
|
|
; X64-NEXT: retq
|
|
%1 = getelementptr inbounds <4 x float>* %pb, i64 %index
|
|
%2 = load <4 x float>* %1, align 16
|
|
%3 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %2, i32 192)
|
|
ret <4 x float> %3
|
|
}
|
|
|
|
define <4 x float> @insertps_from_broadcast_loadf32(<4 x float> %a, float* nocapture readonly %fb, i64 %index) {
|
|
; X32-LABEL: insertps_from_broadcast_loadf32:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
|
; X32-NEXT: movss (%ecx,%eax,4), %xmm1
|
|
; X32-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0]
|
|
; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: insertps_from_broadcast_loadf32:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: movss (%rdi,%rsi,4), %xmm1
|
|
; X64-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0]
|
|
; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
|
|
; X64-NEXT: retq
|
|
%1 = getelementptr inbounds float* %fb, i64 %index
|
|
%2 = load float* %1, align 4
|
|
%3 = insertelement <4 x float> undef, float %2, i32 0
|
|
%4 = insertelement <4 x float> %3, float %2, i32 1
|
|
%5 = insertelement <4 x float> %4, float %2, i32 2
|
|
%6 = insertelement <4 x float> %5, float %2, i32 3
|
|
%7 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %6, i32 48)
|
|
ret <4 x float> %7
|
|
}
|
|
|
|
define <4 x float> @insertps_from_broadcast_loadv4f32(<4 x float> %a, <4 x float>* nocapture readonly %b) {
|
|
; X32-LABEL: insertps_from_broadcast_loadv4f32:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
; X32-NEXT: movups (%eax), %xmm1
|
|
; X32-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0]
|
|
; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: insertps_from_broadcast_loadv4f32:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: movups (%rdi), %xmm1
|
|
; X64-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0,0,0]
|
|
; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm1[0]
|
|
; X64-NEXT: retq
|
|
%1 = load <4 x float>* %b, align 4
|
|
%2 = extractelement <4 x float> %1, i32 0
|
|
%3 = insertelement <4 x float> undef, float %2, i32 0
|
|
%4 = insertelement <4 x float> %3, float %2, i32 1
|
|
%5 = insertelement <4 x float> %4, float %2, i32 2
|
|
%6 = insertelement <4 x float> %5, float %2, i32 3
|
|
%7 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %6, i32 48)
|
|
ret <4 x float> %7
|
|
}
|
|
|
|
;; FIXME: We're emitting an extraneous pshufd/vbroadcast.
|
|
define <4 x float> @insertps_from_broadcast_multiple_use(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d, float* nocapture readonly %fb, i64 %index) {
|
|
; X32-LABEL: insertps_from_broadcast_multiple_use:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
|
; X32-NEXT: movss (%ecx,%eax,4), %xmm4
|
|
; X32-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,0,0,0]
|
|
; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm4[0]
|
|
; X32-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm4[0]
|
|
; X32-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm4[0]
|
|
; X32-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1,2],xmm4[0]
|
|
; X32-NEXT: addps %xmm1, %xmm0
|
|
; X32-NEXT: addps %xmm2, %xmm3
|
|
; X32-NEXT: addps %xmm3, %xmm0
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: insertps_from_broadcast_multiple_use:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: movss (%rdi,%rsi,4), %xmm4
|
|
; X64-NEXT: shufps {{.*#+}} xmm4 = xmm4[0,0,0,0]
|
|
; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],xmm4[0]
|
|
; X64-NEXT: insertps {{.*#+}} xmm1 = xmm1[0,1,2],xmm4[0]
|
|
; X64-NEXT: insertps {{.*#+}} xmm2 = xmm2[0,1,2],xmm4[0]
|
|
; X64-NEXT: insertps {{.*#+}} xmm3 = xmm3[0,1,2],xmm4[0]
|
|
; X64-NEXT: addps %xmm1, %xmm0
|
|
; X64-NEXT: addps %xmm2, %xmm3
|
|
; X64-NEXT: addps %xmm3, %xmm0
|
|
; X64-NEXT: retq
|
|
%1 = getelementptr inbounds float* %fb, i64 %index
|
|
%2 = load float* %1, align 4
|
|
%3 = insertelement <4 x float> undef, float %2, i32 0
|
|
%4 = insertelement <4 x float> %3, float %2, i32 1
|
|
%5 = insertelement <4 x float> %4, float %2, i32 2
|
|
%6 = insertelement <4 x float> %5, float %2, i32 3
|
|
%7 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %a, <4 x float> %6, i32 48)
|
|
%8 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %b, <4 x float> %6, i32 48)
|
|
%9 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %c, <4 x float> %6, i32 48)
|
|
%10 = tail call <4 x float> @llvm.x86.sse41.insertps(<4 x float> %d, <4 x float> %6, i32 48)
|
|
%11 = fadd <4 x float> %7, %8
|
|
%12 = fadd <4 x float> %9, %10
|
|
%13 = fadd <4 x float> %11, %12
|
|
ret <4 x float> %13
|
|
}
|
|
|
|
define <4 x float> @insertps_with_undefs(<4 x float> %a, float* %b) {
|
|
; X32-LABEL: insertps_with_undefs:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
; X32-NEXT: movss (%eax), %xmm1
|
|
; X32-NEXT: insertps {{.*#+}} xmm1 = xmm1[0],zero,xmm0[0],xmm1[3]
|
|
; X32-NEXT: movaps %xmm1, %xmm0
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: insertps_with_undefs:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: movss (%rdi), %xmm1
|
|
; X64-NEXT: insertps {{.*#+}} xmm1 = xmm1[0],zero,xmm0[0],xmm1[3]
|
|
; X64-NEXT: movaps %xmm1, %xmm0
|
|
; X64-NEXT: retq
|
|
%1 = load float* %b, align 4
|
|
%2 = insertelement <4 x float> undef, float %1, i32 0
|
|
%result = shufflevector <4 x float> %a, <4 x float> %2, <4 x i32> <i32 4, i32 undef, i32 0, i32 7>
|
|
ret <4 x float> %result
|
|
}
|
|
|
|
; Test for a bug in X86ISelLowering.cpp:getINSERTPS where we were using
|
|
; the destination index to change the load, instead of the source index.
|
|
define <4 x float> @pr20087(<4 x float> %a, <4 x float> *%ptr) {
|
|
; X32-LABEL: pr20087:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
; X32-NEXT: insertps $-78, 8(%eax), %xmm0
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: pr20087:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: insertps $-78, 8(%rdi), %xmm0
|
|
; X64-NEXT: retq
|
|
%load = load <4 x float> *%ptr
|
|
%ret = shufflevector <4 x float> %load, <4 x float> %a, <4 x i32> <i32 4, i32 undef, i32 6, i32 2>
|
|
ret <4 x float> %ret
|
|
}
|
|
|
|
; Edge case for insertps where we end up with a shuffle with mask=<0, 7, -1, -1>
|
|
define void @insertps_pr20411(i32* noalias nocapture %RET) #1 {
|
|
; X32-LABEL: insertps_pr20411:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
; X32-NEXT: pshufd {{.*#+}} xmm0 = mem[3,1,2,3]
|
|
; X32-NEXT: insertps $-36, LCPI49_1+12, %xmm0
|
|
; X32-NEXT: movups %xmm0, (%eax)
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: insertps_pr20411:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: pshufd {{.*#+}} xmm0 = mem[3,1,2,3]
|
|
; X64-NEXT: insertps $-36, LCPI49_1+{{.*}}(%rip), %xmm0
|
|
; X64-NEXT: movups %xmm0, (%rdi)
|
|
; X64-NEXT: retq
|
|
%gather_load = shufflevector <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>, <8 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
|
%shuffle109 = shufflevector <4 x i32> <i32 4, i32 5, i32 6, i32 7>, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; 4 5 6 7
|
|
%shuffle116 = shufflevector <8 x i32> %gather_load, <8 x i32> undef, <4 x i32> <i32 3, i32 undef, i32 undef, i32 undef> ; 3 x x x
|
|
%shuffle117 = shufflevector <4 x i32> %shuffle109, <4 x i32> %shuffle116, <4 x i32> <i32 4, i32 3, i32 undef, i32 undef> ; 3 7 x x
|
|
%ptrcast = bitcast i32* %RET to <4 x i32>*
|
|
store <4 x i32> %shuffle117, <4 x i32>* %ptrcast, align 4
|
|
ret void
|
|
}
|
|
|
|
define <4 x float> @insertps_4(<4 x float> %A, <4 x float> %B) {
|
|
; X32-LABEL: insertps_4:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm1[2],zero
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: insertps_4:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm1[2],zero
|
|
; X64-NEXT: retq
|
|
entry:
|
|
%vecext = extractelement <4 x float> %A, i32 0
|
|
%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
|
|
%vecinit1 = insertelement <4 x float> %vecinit, float 0.000000e+00, i32 1
|
|
%vecext2 = extractelement <4 x float> %B, i32 2
|
|
%vecinit3 = insertelement <4 x float> %vecinit1, float %vecext2, i32 2
|
|
%vecinit4 = insertelement <4 x float> %vecinit3, float 0.000000e+00, i32 3
|
|
ret <4 x float> %vecinit4
|
|
}
|
|
|
|
define <4 x float> @insertps_5(<4 x float> %A, <4 x float> %B) {
|
|
; X32-LABEL: insertps_5:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[1],zero,zero
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: insertps_5:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[1],zero,zero
|
|
; X64-NEXT: retq
|
|
entry:
|
|
%vecext = extractelement <4 x float> %A, i32 0
|
|
%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
|
|
%vecext1 = extractelement <4 x float> %B, i32 1
|
|
%vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
|
|
%vecinit3 = insertelement <4 x float> %vecinit2, float 0.000000e+00, i32 2
|
|
%vecinit4 = insertelement <4 x float> %vecinit3, float 0.000000e+00, i32 3
|
|
ret <4 x float> %vecinit4
|
|
}
|
|
|
|
define <4 x float> @insertps_6(<4 x float> %A, <4 x float> %B) {
|
|
; X32-LABEL: insertps_6:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[1],xmm1[2],zero
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: insertps_6:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: insertps {{.*#+}} xmm0 = zero,xmm0[1],xmm1[2],zero
|
|
; X64-NEXT: retq
|
|
entry:
|
|
%vecext = extractelement <4 x float> %A, i32 1
|
|
%vecinit = insertelement <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, float %vecext, i32 1
|
|
%vecext1 = extractelement <4 x float> %B, i32 2
|
|
%vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 2
|
|
%vecinit3 = insertelement <4 x float> %vecinit2, float 0.000000e+00, i32 3
|
|
ret <4 x float> %vecinit3
|
|
}
|
|
|
|
define <4 x float> @insertps_7(<4 x float> %A, <4 x float> %B) {
|
|
; X32-LABEL: insertps_7:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm1[1],zero
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: insertps_7:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm1[1],zero
|
|
; X64-NEXT: retq
|
|
entry:
|
|
%vecext = extractelement <4 x float> %A, i32 0
|
|
%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
|
|
%vecinit1 = insertelement <4 x float> %vecinit, float 0.000000e+00, i32 1
|
|
%vecext2 = extractelement <4 x float> %B, i32 1
|
|
%vecinit3 = insertelement <4 x float> %vecinit1, float %vecext2, i32 2
|
|
%vecinit4 = insertelement <4 x float> %vecinit3, float 0.000000e+00, i32 3
|
|
ret <4 x float> %vecinit4
|
|
}
|
|
|
|
define <4 x float> @insertps_8(<4 x float> %A, <4 x float> %B) {
|
|
; X32-LABEL: insertps_8:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],zero,zero
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: insertps_8:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],xmm1[0],zero,zero
|
|
; X64-NEXT: retq
|
|
entry:
|
|
%vecext = extractelement <4 x float> %A, i32 0
|
|
%vecinit = insertelement <4 x float> undef, float %vecext, i32 0
|
|
%vecext1 = extractelement <4 x float> %B, i32 0
|
|
%vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 1
|
|
%vecinit3 = insertelement <4 x float> %vecinit2, float 0.000000e+00, i32 2
|
|
%vecinit4 = insertelement <4 x float> %vecinit3, float 0.000000e+00, i32 3
|
|
ret <4 x float> %vecinit4
|
|
}
|
|
|
|
define <4 x float> @insertps_9(<4 x float> %A, <4 x float> %B) {
|
|
; X32-LABEL: insertps_9:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: insertps {{.*#+}} xmm1 = zero,xmm0[0],xmm1[2],zero
|
|
; X32-NEXT: movaps %xmm1, %xmm0
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: insertps_9:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: insertps {{.*#+}} xmm1 = zero,xmm0[0],xmm1[2],zero
|
|
; X64-NEXT: movaps %xmm1, %xmm0
|
|
; X64-NEXT: retq
|
|
entry:
|
|
%vecext = extractelement <4 x float> %A, i32 0
|
|
%vecinit = insertelement <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, float %vecext, i32 1
|
|
%vecext1 = extractelement <4 x float> %B, i32 2
|
|
%vecinit2 = insertelement <4 x float> %vecinit, float %vecext1, i32 2
|
|
%vecinit3 = insertelement <4 x float> %vecinit2, float 0.000000e+00, i32 3
|
|
ret <4 x float> %vecinit3
|
|
}
|
|
|
|
define <4 x float> @insertps_10(<4 x float> %A)
|
|
{
|
|
; X32-LABEL: insertps_10:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[0],zero
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: insertps_10:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],zero,xmm0[0],zero
|
|
; X64-NEXT: retq
|
|
%vecext = extractelement <4 x float> %A, i32 0
|
|
%vecbuild1 = insertelement <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %vecext, i32 0
|
|
%vecbuild2 = insertelement <4 x float> %vecbuild1, float %vecext, i32 2
|
|
ret <4 x float> %vecbuild2
|
|
}
|
|
|
|
define <4 x float> @build_vector_to_shuffle_1(<4 x float> %A) {
|
|
; X32-LABEL: build_vector_to_shuffle_1:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: xorps %xmm1, %xmm1
|
|
; X32-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: build_vector_to_shuffle_1:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: xorps %xmm1, %xmm1
|
|
; X64-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2],xmm0[3]
|
|
; X64-NEXT: retq
|
|
entry:
|
|
%vecext = extractelement <4 x float> %A, i32 1
|
|
%vecinit = insertelement <4 x float> zeroinitializer, float %vecext, i32 1
|
|
%vecinit1 = insertelement <4 x float> %vecinit, float 0.0, i32 2
|
|
%vecinit3 = shufflevector <4 x float> %vecinit1, <4 x float> %A, <4 x i32> <i32 0, i32 1, i32 2, i32 7>
|
|
ret <4 x float> %vecinit3
|
|
}
|
|
|
|
define <4 x float> @build_vector_to_shuffle_2(<4 x float> %A) {
|
|
; X32-LABEL: build_vector_to_shuffle_2:
|
|
; X32: ## BB#0:
|
|
; X32-NEXT: xorps %xmm1, %xmm1
|
|
; X32-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
|
|
; X32-NEXT: retl
|
|
;
|
|
; X64-LABEL: build_vector_to_shuffle_2:
|
|
; X64: ## BB#0:
|
|
; X64-NEXT: xorps %xmm1, %xmm1
|
|
; X64-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3]
|
|
; X64-NEXT: retq
|
|
entry:
|
|
%vecext = extractelement <4 x float> %A, i32 1
|
|
%vecinit = insertelement <4 x float> zeroinitializer, float %vecext, i32 1
|
|
%vecinit1 = insertelement <4 x float> %vecinit, float 0.0, i32 2
|
|
ret <4 x float> %vecinit1
|
|
}
|