mirror of
https://github.com/c64scene-ar/llvm-6502.git
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922d314e8f
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
48 lines
1.5 KiB
LLVM
48 lines
1.5 KiB
LLVM
; RUN: llc < %s -mcpu=generic -march=x86 | FileCheck %s
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%struct._obstack_chunk = type { i8*, %struct._obstack_chunk*, [4 x i8] }
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%struct.obstack = type { i32, %struct._obstack_chunk*, i8*, i8*, i8*, i32, i32, %struct._obstack_chunk* (...)*, void (...)*, i8*, i8 }
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@stmt_obstack = external global %struct.obstack ; <%struct.obstack*> [#uses=1]
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; This should just not crash.
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define void @test1() nounwind {
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entry:
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br i1 true, label %cond_true, label %cond_next
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cond_true: ; preds = %entry
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%new_size.0.i = select i1 false, i32 0, i32 0 ; <i32> [#uses=1]
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%tmp.i = load i32* bitcast (i8* getelementptr (%struct.obstack* @stmt_obstack, i32 0, i32 10) to i32*) ; <i32> [#uses=1]
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%tmp.i.upgrd.1 = trunc i32 %tmp.i to i8 ; <i8> [#uses=1]
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%tmp21.i = and i8 %tmp.i.upgrd.1, 1 ; <i8> [#uses=1]
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%tmp22.i = icmp eq i8 %tmp21.i, 0 ; <i1> [#uses=1]
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br i1 %tmp22.i, label %cond_false30.i, label %cond_true23.i
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cond_true23.i: ; preds = %cond_true
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ret void
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cond_false30.i: ; preds = %cond_true
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%tmp35.i = tail call %struct._obstack_chunk* null( i32 %new_size.0.i ) ; <%struct._obstack_chunk*> [#uses=0]
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ret void
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cond_next: ; preds = %entry
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ret void
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}
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define i32 @test2(i16* %P, i16* %Q) nounwind {
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%A = load i16* %P, align 4 ; <i16> [#uses=11]
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%C = zext i16 %A to i32 ; <i32> [#uses=1]
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%D = and i32 %C, 255 ; <i32> [#uses=1]
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br label %L
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L:
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store i16 %A, i16* %Q
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ret i32 %D
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; CHECK: test2:
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; CHECK: movl 4(%esp), %eax
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; CHECK-NEXT: movzwl (%eax), %ecx
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}
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