mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-27 15:29:51 +00:00
3bf9125933
addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106243 91177308-0d34-0410-b5e6-96231b3b80d8
642 lines
22 KiB
C++
642 lines
22 KiB
C++
//===- SystemZInstrInfo.cpp - SystemZ Instruction Information --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SystemZ implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZ.h"
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#include "SystemZInstrBuilder.h"
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#include "SystemZInstrInfo.h"
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#include "SystemZMachineFunctionInfo.h"
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#include "SystemZTargetMachine.h"
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#include "SystemZGenInstrInfo.inc"
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#include "llvm/Function.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/PseudoSourceValue.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)
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: TargetInstrInfoImpl(SystemZInsts, array_lengthof(SystemZInsts)),
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RI(tm, *this), TM(tm) {
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// Fill the spill offsets map
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static const unsigned SpillOffsTab[][2] = {
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{ SystemZ::R2D, 0x10 },
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{ SystemZ::R3D, 0x18 },
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{ SystemZ::R4D, 0x20 },
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{ SystemZ::R5D, 0x28 },
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{ SystemZ::R6D, 0x30 },
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{ SystemZ::R7D, 0x38 },
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{ SystemZ::R8D, 0x40 },
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{ SystemZ::R9D, 0x48 },
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{ SystemZ::R10D, 0x50 },
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{ SystemZ::R11D, 0x58 },
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{ SystemZ::R12D, 0x60 },
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{ SystemZ::R13D, 0x68 },
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{ SystemZ::R14D, 0x70 },
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{ SystemZ::R15D, 0x78 }
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};
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RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS);
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for (unsigned i = 0, e = array_lengthof(SpillOffsTab); i != e; ++i)
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RegSpillOffsets[SpillOffsTab[i][0]] = SpillOffsTab[i][1];
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}
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/// isGVStub - Return true if the GV requires an extra load to get the
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/// real address.
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static inline bool isGVStub(GlobalValue *GV, SystemZTargetMachine &TM) {
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return TM.getSubtarget<SystemZSubtarget>().GVRequiresExtraLoad(GV, TM, false);
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}
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void SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill, int FrameIdx,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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unsigned Opc = 0;
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if (RC == &SystemZ::GR32RegClass ||
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RC == &SystemZ::ADDR32RegClass)
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Opc = SystemZ::MOV32mr;
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else if (RC == &SystemZ::GR64RegClass ||
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RC == &SystemZ::ADDR64RegClass) {
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Opc = SystemZ::MOV64mr;
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} else if (RC == &SystemZ::FP32RegClass) {
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Opc = SystemZ::FMOV32mr;
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} else if (RC == &SystemZ::FP64RegClass) {
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Opc = SystemZ::FMOV64mr;
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} else if (RC == &SystemZ::GR64PRegClass) {
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Opc = SystemZ::MOV64Pmr;
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} else if (RC == &SystemZ::GR128RegClass) {
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Opc = SystemZ::MOV128mr;
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} else
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llvm_unreachable("Unsupported regclass to store");
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addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
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.addReg(SrcReg, getKillRegState(isKill));
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}
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void SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const{
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DebugLoc DL;
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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unsigned Opc = 0;
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if (RC == &SystemZ::GR32RegClass ||
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RC == &SystemZ::ADDR32RegClass)
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Opc = SystemZ::MOV32rm;
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else if (RC == &SystemZ::GR64RegClass ||
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RC == &SystemZ::ADDR64RegClass) {
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Opc = SystemZ::MOV64rm;
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} else if (RC == &SystemZ::FP32RegClass) {
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Opc = SystemZ::FMOV32rm;
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} else if (RC == &SystemZ::FP64RegClass) {
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Opc = SystemZ::FMOV64rm;
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} else if (RC == &SystemZ::GR64PRegClass) {
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Opc = SystemZ::MOV64Prm;
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} else if (RC == &SystemZ::GR128RegClass) {
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Opc = SystemZ::MOV128rm;
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} else
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llvm_unreachable("Unsupported regclass to load");
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addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
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}
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bool SystemZInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC,
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DebugLoc DL) const {
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// Determine if DstRC and SrcRC have a common superclass.
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const TargetRegisterClass *CommonRC = DestRC;
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if (DestRC == SrcRC)
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/* Same regclass for source and dest */;
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else if (CommonRC->hasSuperClass(SrcRC))
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CommonRC = SrcRC;
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else if (!CommonRC->hasSubClass(SrcRC))
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CommonRC = 0;
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if (CommonRC) {
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if (CommonRC == &SystemZ::GR64RegClass ||
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CommonRC == &SystemZ::ADDR64RegClass) {
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BuildMI(MBB, I, DL, get(SystemZ::MOV64rr), DestReg).addReg(SrcReg);
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} else if (CommonRC == &SystemZ::GR32RegClass ||
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CommonRC == &SystemZ::ADDR32RegClass) {
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BuildMI(MBB, I, DL, get(SystemZ::MOV32rr), DestReg).addReg(SrcReg);
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} else if (CommonRC == &SystemZ::GR64PRegClass) {
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BuildMI(MBB, I, DL, get(SystemZ::MOV64rrP), DestReg).addReg(SrcReg);
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} else if (CommonRC == &SystemZ::GR128RegClass) {
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BuildMI(MBB, I, DL, get(SystemZ::MOV128rr), DestReg).addReg(SrcReg);
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} else if (CommonRC == &SystemZ::FP32RegClass) {
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BuildMI(MBB, I, DL, get(SystemZ::FMOV32rr), DestReg).addReg(SrcReg);
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} else if (CommonRC == &SystemZ::FP64RegClass) {
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BuildMI(MBB, I, DL, get(SystemZ::FMOV64rr), DestReg).addReg(SrcReg);
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} else {
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return false;
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}
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return true;
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}
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if ((SrcRC == &SystemZ::GR64RegClass &&
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DestRC == &SystemZ::ADDR64RegClass) ||
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(DestRC == &SystemZ::GR64RegClass &&
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SrcRC == &SystemZ::ADDR64RegClass)) {
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BuildMI(MBB, I, DL, get(SystemZ::MOV64rr), DestReg).addReg(SrcReg);
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return true;
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} else if ((SrcRC == &SystemZ::GR32RegClass &&
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DestRC == &SystemZ::ADDR32RegClass) ||
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(DestRC == &SystemZ::GR32RegClass &&
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SrcRC == &SystemZ::ADDR32RegClass)) {
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BuildMI(MBB, I, DL, get(SystemZ::MOV32rr), DestReg).addReg(SrcReg);
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return true;
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}
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return false;
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}
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bool
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SystemZInstrInfo::isMoveInstr(const MachineInstr& MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
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switch (MI.getOpcode()) {
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default:
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return false;
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case SystemZ::MOV32rr:
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case SystemZ::MOV64rr:
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case SystemZ::MOV64rrP:
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case SystemZ::MOV128rr:
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case SystemZ::FMOV32rr:
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case SystemZ::FMOV64rr:
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assert(MI.getNumOperands() >= 2 &&
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MI.getOperand(0).isReg() &&
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MI.getOperand(1).isReg() &&
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"invalid register-register move instruction");
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SrcReg = MI.getOperand(1).getReg();
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DstReg = MI.getOperand(0).getReg();
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SrcSubIdx = MI.getOperand(1).getSubReg();
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DstSubIdx = MI.getOperand(0).getSubReg();
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return true;
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}
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}
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unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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switch (MI->getOpcode()) {
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default: break;
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case SystemZ::MOV32rm:
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case SystemZ::MOV32rmy:
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case SystemZ::MOV64rm:
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case SystemZ::MOVSX32rm8:
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case SystemZ::MOVSX32rm16y:
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case SystemZ::MOVSX64rm8:
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case SystemZ::MOVSX64rm16:
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case SystemZ::MOVSX64rm32:
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case SystemZ::MOVZX32rm8:
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case SystemZ::MOVZX32rm16:
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case SystemZ::MOVZX64rm8:
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case SystemZ::MOVZX64rm16:
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case SystemZ::MOVZX64rm32:
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case SystemZ::FMOV32rm:
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case SystemZ::FMOV32rmy:
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case SystemZ::FMOV64rm:
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case SystemZ::FMOV64rmy:
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case SystemZ::MOV64Prm:
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case SystemZ::MOV64Prmy:
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case SystemZ::MOV128rm:
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if (MI->getOperand(1).isFI() &&
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MI->getOperand(2).isImm() && MI->getOperand(3).isReg() &&
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MI->getOperand(2).getImm() == 0 && MI->getOperand(3).getReg() == 0) {
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FrameIndex = MI->getOperand(1).getIndex();
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return MI->getOperand(0).getReg();
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}
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break;
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}
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return 0;
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}
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unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const {
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switch (MI->getOpcode()) {
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default: break;
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case SystemZ::MOV32mr:
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case SystemZ::MOV32mry:
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case SystemZ::MOV64mr:
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case SystemZ::MOV32m8r:
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case SystemZ::MOV32m8ry:
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case SystemZ::MOV32m16r:
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case SystemZ::MOV32m16ry:
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case SystemZ::MOV64m8r:
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case SystemZ::MOV64m8ry:
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case SystemZ::MOV64m16r:
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case SystemZ::MOV64m16ry:
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case SystemZ::MOV64m32r:
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case SystemZ::MOV64m32ry:
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case SystemZ::FMOV32mr:
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case SystemZ::FMOV32mry:
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case SystemZ::FMOV64mr:
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case SystemZ::FMOV64mry:
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case SystemZ::MOV64Pmr:
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case SystemZ::MOV64Pmry:
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case SystemZ::MOV128mr:
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if (MI->getOperand(0).isFI() &&
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MI->getOperand(1).isImm() && MI->getOperand(2).isReg() &&
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MI->getOperand(1).getImm() == 0 && MI->getOperand(2).getReg() == 0) {
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FrameIndex = MI->getOperand(0).getIndex();
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return MI->getOperand(3).getReg();
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}
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break;
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}
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return 0;
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}
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bool
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SystemZInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const {
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if (CSI.empty())
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return false;
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DebugLoc DL;
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>();
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unsigned CalleeFrameSize = 0;
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// Scan the callee-saved and find the bounds of register spill area.
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unsigned LowReg = 0, HighReg = 0, StartOffset = -1U, EndOffset = 0;
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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if (!SystemZ::FP64RegClass.contains(Reg)) {
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unsigned Offset = RegSpillOffsets[Reg];
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CalleeFrameSize += 8;
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if (StartOffset > Offset) {
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LowReg = Reg; StartOffset = Offset;
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}
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if (EndOffset < Offset) {
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HighReg = Reg; EndOffset = RegSpillOffsets[Reg];
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}
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}
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}
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// Save information for epilogue inserter.
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MFI->setCalleeSavedFrameSize(CalleeFrameSize);
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MFI->setLowReg(LowReg); MFI->setHighReg(HighReg);
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// Save GPRs
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if (StartOffset) {
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// Build a store instruction. Use STORE MULTIPLE instruction if there are many
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// registers to store, otherwise - just STORE.
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MachineInstrBuilder MIB =
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BuildMI(MBB, MI, DL, get((LowReg == HighReg ?
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SystemZ::MOV64mr : SystemZ::MOV64mrm)));
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// Add store operands.
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MIB.addReg(SystemZ::R15D).addImm(StartOffset);
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if (LowReg == HighReg)
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MIB.addReg(0);
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MIB.addReg(LowReg, RegState::Kill);
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if (LowReg != HighReg)
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MIB.addReg(HighReg, RegState::Kill);
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// Do a second scan adding regs as being killed by instruction
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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// Add the callee-saved register as live-in. It's killed at the spill.
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MBB.addLiveIn(Reg);
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if (Reg != LowReg && Reg != HighReg)
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MIB.addReg(Reg, RegState::ImplicitKill);
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}
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}
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// Save FPRs
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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if (SystemZ::FP64RegClass.contains(Reg)) {
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MBB.addLiveIn(Reg);
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storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(),
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&SystemZ::FP64RegClass, &RI);
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}
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}
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return true;
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}
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bool
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SystemZInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const {
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if (CSI.empty())
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return false;
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DebugLoc DL;
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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MachineFunction &MF = *MBB.getParent();
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const TargetRegisterInfo *RegInfo= MF.getTarget().getRegisterInfo();
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SystemZMachineFunctionInfo *MFI = MF.getInfo<SystemZMachineFunctionInfo>();
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// Restore FP registers
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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if (SystemZ::FP64RegClass.contains(Reg))
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loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(),
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&SystemZ::FP64RegClass, &RI);
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}
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// Restore GP registers
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unsigned LowReg = MFI->getLowReg(), HighReg = MFI->getHighReg();
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unsigned StartOffset = RegSpillOffsets[LowReg];
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if (StartOffset) {
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// Build a load instruction. Use LOAD MULTIPLE instruction if there are many
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// registers to load, otherwise - just LOAD.
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MachineInstrBuilder MIB =
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BuildMI(MBB, MI, DL, get((LowReg == HighReg ?
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SystemZ::MOV64rm : SystemZ::MOV64rmm)));
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// Add store operands.
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MIB.addReg(LowReg, RegState::Define);
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if (LowReg != HighReg)
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MIB.addReg(HighReg, RegState::Define);
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MIB.addReg((RegInfo->hasFP(MF) ? SystemZ::R11D : SystemZ::R15D));
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MIB.addImm(StartOffset);
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if (LowReg == HighReg)
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MIB.addReg(0);
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// Do a second scan adding regs as being defined by instruction
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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unsigned Reg = CSI[i].getReg();
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if (Reg != LowReg && Reg != HighReg)
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MIB.addReg(Reg, RegState::ImplicitDefine);
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}
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}
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return true;
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}
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bool SystemZInstrInfo::
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ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
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assert(Cond.size() == 1 && "Invalid Xbranch condition!");
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SystemZCC::CondCodes CC = static_cast<SystemZCC::CondCodes>(Cond[0].getImm());
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Cond[0].setImm(getOppositeCondition(CC));
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return false;
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}
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bool SystemZInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
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const TargetInstrDesc &TID = MI->getDesc();
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if (!TID.isTerminator()) return false;
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// Conditional branch is a special case.
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if (TID.isBranch() && !TID.isBarrier())
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return true;
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if (!TID.isPredicable())
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return true;
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return !isPredicated(MI);
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}
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bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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// Start from the bottom of the block and work up, examining the
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// terminator instructions.
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MachineBasicBlock::iterator I = MBB.end();
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while (I != MBB.begin()) {
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--I;
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if (I->isDebugValue())
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continue;
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// Working from the bottom, when we see a non-terminator
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// instruction, we're done.
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if (!isUnpredicatedTerminator(I))
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break;
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// A terminator that isn't a branch can't easily be handled
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// by this analysis.
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if (!I->getDesc().isBranch())
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return true;
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// Handle unconditional branches.
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if (I->getOpcode() == SystemZ::JMP) {
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if (!AllowModify) {
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TBB = I->getOperand(0).getMBB();
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continue;
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}
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// If the block has any instructions after a JMP, delete them.
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while (llvm::next(I) != MBB.end())
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llvm::next(I)->eraseFromParent();
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Cond.clear();
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FBB = 0;
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// Delete the JMP if it's equivalent to a fall-through.
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if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
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TBB = 0;
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I->eraseFromParent();
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I = MBB.end();
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continue;
|
|
}
|
|
|
|
// TBB is used to indicate the unconditinal destination.
|
|
TBB = I->getOperand(0).getMBB();
|
|
continue;
|
|
}
|
|
|
|
// Handle conditional branches.
|
|
SystemZCC::CondCodes BranchCode = getCondFromBranchOpc(I->getOpcode());
|
|
if (BranchCode == SystemZCC::INVALID)
|
|
return true; // Can't handle indirect branch.
|
|
|
|
// Working from the bottom, handle the first conditional branch.
|
|
if (Cond.empty()) {
|
|
FBB = TBB;
|
|
TBB = I->getOperand(0).getMBB();
|
|
Cond.push_back(MachineOperand::CreateImm(BranchCode));
|
|
continue;
|
|
}
|
|
|
|
// Handle subsequent conditional branches. Only handle the case where all
|
|
// conditional branches branch to the same destination.
|
|
assert(Cond.size() == 1);
|
|
assert(TBB);
|
|
|
|
// Only handle the case where all conditional branches branch to
|
|
// the same destination.
|
|
if (TBB != I->getOperand(0).getMBB())
|
|
return true;
|
|
|
|
SystemZCC::CondCodes OldBranchCode = (SystemZCC::CondCodes)Cond[0].getImm();
|
|
// If the conditions are the same, we can leave them alone.
|
|
if (OldBranchCode == BranchCode)
|
|
continue;
|
|
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
|
|
MachineBasicBlock::iterator I = MBB.end();
|
|
unsigned Count = 0;
|
|
|
|
while (I != MBB.begin()) {
|
|
--I;
|
|
if (I->isDebugValue())
|
|
continue;
|
|
if (I->getOpcode() != SystemZ::JMP &&
|
|
getCondFromBranchOpc(I->getOpcode()) == SystemZCC::INVALID)
|
|
break;
|
|
// Remove the branch.
|
|
I->eraseFromParent();
|
|
I = MBB.end();
|
|
++Count;
|
|
}
|
|
|
|
return Count;
|
|
}
|
|
|
|
unsigned
|
|
SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
|
MachineBasicBlock *FBB,
|
|
const SmallVectorImpl<MachineOperand> &Cond,
|
|
DebugLoc DL) const {
|
|
// Shouldn't be a fall through.
|
|
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
|
|
assert((Cond.size() == 1 || Cond.size() == 0) &&
|
|
"SystemZ branch conditions have one component!");
|
|
|
|
if (Cond.empty()) {
|
|
// Unconditional branch?
|
|
assert(!FBB && "Unconditional branch with multiple successors!");
|
|
BuildMI(&MBB, DL, get(SystemZ::JMP)).addMBB(TBB);
|
|
return 1;
|
|
}
|
|
|
|
// Conditional branch.
|
|
unsigned Count = 0;
|
|
SystemZCC::CondCodes CC = (SystemZCC::CondCodes)Cond[0].getImm();
|
|
BuildMI(&MBB, DL, getBrCond(CC)).addMBB(TBB);
|
|
++Count;
|
|
|
|
if (FBB) {
|
|
// Two-way Conditional branch. Insert the second branch.
|
|
BuildMI(&MBB, DL, get(SystemZ::JMP)).addMBB(FBB);
|
|
++Count;
|
|
}
|
|
return Count;
|
|
}
|
|
|
|
const TargetInstrDesc&
|
|
SystemZInstrInfo::getBrCond(SystemZCC::CondCodes CC) const {
|
|
switch (CC) {
|
|
default:
|
|
llvm_unreachable("Unknown condition code!");
|
|
case SystemZCC::O: return get(SystemZ::JO);
|
|
case SystemZCC::H: return get(SystemZ::JH);
|
|
case SystemZCC::NLE: return get(SystemZ::JNLE);
|
|
case SystemZCC::L: return get(SystemZ::JL);
|
|
case SystemZCC::NHE: return get(SystemZ::JNHE);
|
|
case SystemZCC::LH: return get(SystemZ::JLH);
|
|
case SystemZCC::NE: return get(SystemZ::JNE);
|
|
case SystemZCC::E: return get(SystemZ::JE);
|
|
case SystemZCC::NLH: return get(SystemZ::JNLH);
|
|
case SystemZCC::HE: return get(SystemZ::JHE);
|
|
case SystemZCC::NL: return get(SystemZ::JNL);
|
|
case SystemZCC::LE: return get(SystemZ::JLE);
|
|
case SystemZCC::NH: return get(SystemZ::JNH);
|
|
case SystemZCC::NO: return get(SystemZ::JNO);
|
|
}
|
|
}
|
|
|
|
SystemZCC::CondCodes
|
|
SystemZInstrInfo::getCondFromBranchOpc(unsigned Opc) const {
|
|
switch (Opc) {
|
|
default: return SystemZCC::INVALID;
|
|
case SystemZ::JO: return SystemZCC::O;
|
|
case SystemZ::JH: return SystemZCC::H;
|
|
case SystemZ::JNLE: return SystemZCC::NLE;
|
|
case SystemZ::JL: return SystemZCC::L;
|
|
case SystemZ::JNHE: return SystemZCC::NHE;
|
|
case SystemZ::JLH: return SystemZCC::LH;
|
|
case SystemZ::JNE: return SystemZCC::NE;
|
|
case SystemZ::JE: return SystemZCC::E;
|
|
case SystemZ::JNLH: return SystemZCC::NLH;
|
|
case SystemZ::JHE: return SystemZCC::HE;
|
|
case SystemZ::JNL: return SystemZCC::NL;
|
|
case SystemZ::JLE: return SystemZCC::LE;
|
|
case SystemZ::JNH: return SystemZCC::NH;
|
|
case SystemZ::JNO: return SystemZCC::NO;
|
|
}
|
|
}
|
|
|
|
SystemZCC::CondCodes
|
|
SystemZInstrInfo::getOppositeCondition(SystemZCC::CondCodes CC) const {
|
|
switch (CC) {
|
|
default:
|
|
llvm_unreachable("Invalid condition!");
|
|
case SystemZCC::O: return SystemZCC::NO;
|
|
case SystemZCC::H: return SystemZCC::NH;
|
|
case SystemZCC::NLE: return SystemZCC::LE;
|
|
case SystemZCC::L: return SystemZCC::NL;
|
|
case SystemZCC::NHE: return SystemZCC::HE;
|
|
case SystemZCC::LH: return SystemZCC::NLH;
|
|
case SystemZCC::NE: return SystemZCC::E;
|
|
case SystemZCC::E: return SystemZCC::NE;
|
|
case SystemZCC::NLH: return SystemZCC::LH;
|
|
case SystemZCC::HE: return SystemZCC::NHE;
|
|
case SystemZCC::NL: return SystemZCC::L;
|
|
case SystemZCC::LE: return SystemZCC::NLE;
|
|
case SystemZCC::NH: return SystemZCC::H;
|
|
case SystemZCC::NO: return SystemZCC::O;
|
|
}
|
|
}
|
|
|
|
const TargetInstrDesc&
|
|
SystemZInstrInfo::getLongDispOpc(unsigned Opc) const {
|
|
switch (Opc) {
|
|
default:
|
|
llvm_unreachable("Don't have long disp version of this instruction");
|
|
case SystemZ::MOV32mr: return get(SystemZ::MOV32mry);
|
|
case SystemZ::MOV32rm: return get(SystemZ::MOV32rmy);
|
|
case SystemZ::MOVSX32rm16: return get(SystemZ::MOVSX32rm16y);
|
|
case SystemZ::MOV32m8r: return get(SystemZ::MOV32m8ry);
|
|
case SystemZ::MOV32m16r: return get(SystemZ::MOV32m16ry);
|
|
case SystemZ::MOV64m8r: return get(SystemZ::MOV64m8ry);
|
|
case SystemZ::MOV64m16r: return get(SystemZ::MOV64m16ry);
|
|
case SystemZ::MOV64m32r: return get(SystemZ::MOV64m32ry);
|
|
case SystemZ::MOV8mi: return get(SystemZ::MOV8miy);
|
|
case SystemZ::MUL32rm: return get(SystemZ::MUL32rmy);
|
|
case SystemZ::CMP32rm: return get(SystemZ::CMP32rmy);
|
|
case SystemZ::UCMP32rm: return get(SystemZ::UCMP32rmy);
|
|
case SystemZ::FMOV32mr: return get(SystemZ::FMOV32mry);
|
|
case SystemZ::FMOV64mr: return get(SystemZ::FMOV64mry);
|
|
case SystemZ::FMOV32rm: return get(SystemZ::FMOV32rmy);
|
|
case SystemZ::FMOV64rm: return get(SystemZ::FMOV64rmy);
|
|
case SystemZ::MOV64Pmr: return get(SystemZ::MOV64Pmry);
|
|
case SystemZ::MOV64Prm: return get(SystemZ::MOV64Prmy);
|
|
}
|
|
}
|