Alex Lorenz 328f462f3c MIR Serialization: print and parse LLVM IR using MIR format. ... This commit is the initial commit for the MIR serialization project. It creates a new library under CodeGen called 'MIR'. This new library adds a new machine function pass that prints out the LLVM IR using the MIR format. This pass is then added as a last pass when a 'stop-after' option is used in llc. The new library adds the initial functionality for parsing of MIR files as well. This commit also extends the llc tool so that it can recognize and parse MIR input files. Reviewers: Duncan P. N. Exon Smith, Matthias Braun, Philip Reames Differential Revision: http://reviews.llvm.org/D9616 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237708 91177308-0d34-0410-b5e6-96231b3b80d8		2015-05-19 18:17:39 +00:00
..
AArch64	Revert r237579, as it broke windows buildbots	2015-05-18 16:39:16 +00:00
ARM	ARM: allow jump tables to be placed as constant islands.	2015-05-18 17:10:40 +00:00
BPF	[opaque pointer type] Add textual IR support for explicit type parameter to the call instruction	2015-04-16 23:24:18 +00:00
CPP	[opaque pointer type] Add textual IR support for explicit type parameter to the call instruction	2015-04-16 23:24:18 +00:00
Generic	MIR Serialization: print and parse LLVM IR using MIR format.	2015-05-19 18:17:39 +00:00
Hexagon	[Hexagon] Generate hardware loop for a vectorized loop	2015-05-14 20:36:19 +00:00
Inputs	IR: Give 'DI' prefix to debug info metadata	2015-04-29 16:38:44 +00:00
Mips	[mips] Correct and improve special-case shuffle instructions.	2015-05-19 12:24:52 +00:00
MIR	MIR Serialization: print and parse LLVM IR using MIR format.	2015-05-19 18:17:39 +00:00
MSP430	[opaque pointer type] Add textual IR support for explicit type parameter to gep operator	2015-03-13 18:20:45 +00:00
NVPTX	[NVPTX] Handle addrspacecast constant expressions in aggregate initializers	2015-04-28 17:18:30 +00:00
PowerPC	[PowerPC] Add extra r2 read deps on @toc@l relocations	2015-05-18 06:25:59 +00:00
R600	R600/SI: add pass to mark CF live ranges as non-spillable	2015-05-12 17:13:02 +00:00
SPARC	Add support for the Sparc implementation-defined "ASR" registers.	2015-05-18 16:29:48 +00:00
SystemZ	[DAGCombiner] Account for getVectorIdxTy() when narrowing vector load	2015-05-05 19:34:10 +00:00
Thumb	IR: Give 'DI' prefix to debug info metadata	2015-04-29 16:38:44 +00:00
Thumb2	ARM: allow jump tables to be placed as constant islands.	2015-05-18 17:10:40 +00:00
WinEH	Changed renaming of local symbols by inserting a dot vefore the numeric suffix.	2015-05-12 16:47:30 +00:00
X86	[X86] ABI change for x86-32: pass 3 vector arguments in-register instead of 4, except on Darwin.	2015-05-19 11:06:56 +00:00
XCore	IR: Give 'DI' prefix to debug info metadata	2015-04-29 16:38:44 +00:00