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f20db15954
machine instr will change its definition register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47166 91177308-0d34-0410-b5e6-96231b3b80d8
405 lines
18 KiB
C++
405 lines
18 KiB
C++
//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the target machine instructions to the code generator.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_TARGETINSTRINFO_H
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#define LLVM_TARGET_TARGETINSTRINFO_H
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#include "llvm/Target/TargetInstrDesc.h"
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#include "llvm/CodeGen/MachineFunction.h"
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namespace llvm {
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class TargetRegisterClass;
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class LiveVariables;
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class CalleeSavedInfo;
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class SDNode;
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class SelectionDAG;
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template<class T> class SmallVectorImpl;
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//---------------------------------------------------------------------------
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///
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/// TargetInstrInfo - Interface to description of machine instructions
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///
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class TargetInstrInfo {
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const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
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unsigned NumOpcodes; // Number of entries in the desc array
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TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
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void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
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public:
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TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
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virtual ~TargetInstrInfo();
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// Invariant opcodes: All instruction sets have these as their low opcodes.
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enum {
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PHI = 0,
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INLINEASM = 1,
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LABEL = 2,
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DECLARE = 3,
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EXTRACT_SUBREG = 4,
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INSERT_SUBREG = 5
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};
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unsigned getNumOpcodes() const { return NumOpcodes; }
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/// get - Return the machine instruction descriptor that corresponds to the
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/// specified instruction opcode.
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///
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const TargetInstrDesc &get(unsigned Opcode) const {
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assert(Opcode < NumOpcodes && "Invalid opcode!");
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return Descriptors[Opcode];
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}
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/// isTriviallyReMaterializable - Return true if the instruction is trivially
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/// rematerializable, meaning it has no side effects and requires no operands
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/// that aren't always available.
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bool isTriviallyReMaterializable(MachineInstr *MI) const {
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return MI->getDesc().isRematerializable() &&
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isReallyTriviallyReMaterializable(MI);
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}
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protected:
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/// isReallyTriviallyReMaterializable - For instructions with opcodes for
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/// which the M_REMATERIALIZABLE flag is set, this function tests whether the
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/// instruction itself is actually trivially rematerializable, considering
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/// its operands. This is used for targets that have instructions that are
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/// only trivially rematerializable for specific uses. This predicate must
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/// return false if the instruction has any side effects other than
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/// producing a value, or if it requres any address registers that are not
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/// always available.
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virtual bool isReallyTriviallyReMaterializable(MachineInstr *MI) const {
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return true;
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}
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public:
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/// Return true if the instruction is a register to register move
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/// and leave the source and dest operands in the passed parameters.
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virtual bool isMoveInstr(const MachineInstr& MI,
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unsigned& sourceReg,
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unsigned& destReg) const {
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return false;
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}
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const{
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return 0;
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}
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const {
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return 0;
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}
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/// isInvariantLoad - Return true if the specified instruction (which is
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/// marked mayLoad) is loading from a location whose value is invariant across
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/// the function. For example, loading a value from the constant pool or from
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/// from the argument area of a function if it does not change. This should
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/// only return true of *all* loads the instruction does are invariant (if it
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/// does multiple loads).
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virtual bool isInvariantLoad(MachineInstr *MI) const {
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return false;
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}
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/// convertToThreeAddress - This method must be implemented by targets that
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/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
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/// may be able to convert a two-address instruction into one or more true
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/// three-address instructions on demand. This allows the X86 target (for
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/// example) to convert ADD and SHL instructions into LEA instructions if they
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/// would require register copies due to two-addressness.
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///
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/// This method returns a null pointer if the transformation cannot be
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/// performed, otherwise it returns the last new instruction.
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///
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virtual MachineInstr *
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convertToThreeAddress(MachineFunction::iterator &MFI,
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MachineBasicBlock::iterator &MBBI, LiveVariables &LV) const {
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return 0;
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}
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/// commuteInstruction - If a target has any instructions that are commutable,
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/// but require converting to a different instruction or making non-trivial
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/// changes to commute them, this method can overloaded to do this. The
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/// default implementation of this method simply swaps the first two operands
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/// of MI and returns it.
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///
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/// If a target wants to make more aggressive changes, they can construct and
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/// return a new machine instruction. If an instruction cannot commute, it
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/// can also return null.
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///
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virtual MachineInstr *commuteInstruction(MachineInstr *MI) const = 0;
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/// CommuteChangesDestination - Return true if commuting the specified
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/// instruction will also changes the destination operand. Also return the
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/// current operand index of the would be new destination register by
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/// reference. This can happen when the commutable instruction is also a
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/// two-address instruction.
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virtual bool CommuteChangesDestination(MachineInstr *MI,
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unsigned &OpIdx) const = 0;
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/// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
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/// true if it cannot be understood (e.g. it's a switch dispatch or isn't
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/// implemented for a target). Upon success, this returns false and returns
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/// with the following information in various cases:
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///
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/// 1. If this block ends with no branches (it just falls through to its succ)
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/// just return false, leaving TBB/FBB null.
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/// 2. If this block ends with only an unconditional branch, it sets TBB to be
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/// the destination block.
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/// 3. If this block ends with an conditional branch and it falls through to
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/// an successor block, it sets TBB to be the branch destination block and a
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/// list of operands that evaluate the condition. These
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/// operands can be passed to other TargetInstrInfo methods to create new
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/// branches.
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/// 4. If this block ends with an conditional branch and an unconditional
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/// block, it returns the 'true' destination in TBB, the 'false' destination
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/// in FBB, and a list of operands that evaluate the condition. These
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/// operands can be passed to other TargetInstrInfo methods to create new
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/// branches.
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///
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/// Note that RemoveBranch and InsertBranch must be implemented to support
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/// cases where this method returns success.
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///
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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std::vector<MachineOperand> &Cond) const {
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return true;
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}
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/// RemoveBranch - Remove the branching code at the end of the specific MBB.
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/// this is only invoked in cases where AnalyzeBranch returns success. It
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/// returns the number of instructions that were removed.
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const {
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assert(0 && "Target didn't implement TargetInstrInfo::RemoveBranch!");
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return 0;
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}
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/// InsertBranch - Insert a branch into the end of the specified
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/// MachineBasicBlock. This operands to this method are the same as those
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/// returned by AnalyzeBranch. This is invoked in cases where AnalyzeBranch
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/// returns success and when an unconditional branch (TBB is non-null, FBB is
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/// null, Cond is empty) needs to be inserted. It returns the number of
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/// instructions inserted.
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const std::vector<MachineOperand> &Cond) const {
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assert(0 && "Target didn't implement TargetInstrInfo::InsertBranch!");
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return 0;
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}
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/// copyRegToReg - Add a copy between a pair of registers
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virtual void copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const {
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assert(0 && "Target didn't implement TargetInstrInfo::copyRegToReg!");
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}
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virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC) const {
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assert(0 && "Target didn't implement TargetInstrInfo::storeRegToStackSlot!");
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}
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virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const {
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assert(0 && "Target didn't implement TargetInstrInfo::storeRegToAddr!");
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}
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virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC) const {
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assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
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}
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virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const {
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assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!");
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}
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/// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
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/// saved registers and returns true if it isn't possible / profitable to do
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/// so by issuing a series of store instructions via
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/// storeRegToStackSlot(). Returns false otherwise.
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virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI) const {
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return false;
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}
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/// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
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/// saved registers and returns true if it isn't possible / profitable to do
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/// so by issuing a series of load instructions via loadRegToStackSlot().
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/// Returns false otherwise.
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virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI) const {
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return false;
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}
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/// foldMemoryOperand - Attempt to fold a load or store of the specified stack
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/// slot into the specified machine instruction for the specified operand(s).
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/// If this is possible, a new instruction is returned with the specified
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/// operand folded, otherwise NULL is returned. The client is responsible for
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/// removing the old instruction and adding the new one in the instruction
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/// stream.
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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MachineInstr* MI,
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SmallVectorImpl<unsigned> &Ops,
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int FrameIndex) const {
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return 0;
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}
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/// foldMemoryOperand - Same as the previous version except it allows folding
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/// of any load and store from / to any address, not just from a specific
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/// stack slot.
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virtual MachineInstr* foldMemoryOperand(MachineFunction &MF,
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MachineInstr* MI,
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SmallVectorImpl<unsigned> &Ops,
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MachineInstr* LoadMI) const {
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return 0;
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}
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/// canFoldMemoryOperand - Returns true if the specified load / store is
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/// folding is possible.
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virtual
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bool canFoldMemoryOperand(MachineInstr *MI,
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SmallVectorImpl<unsigned> &Ops) const{
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return false;
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}
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/// unfoldMemoryOperand - Separate a single instruction which folded a load or
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/// a store or a load and a store into two or more instruction. If this is
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/// possible, returns true as well as the new instructions by reference.
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virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
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unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
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SmallVectorImpl<MachineInstr*> &NewMIs) const{
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return false;
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}
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virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
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SmallVectorImpl<SDNode*> &NewNodes) const {
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return false;
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}
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/// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
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/// instruction after load / store are unfolded from an instruction of the
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/// specified opcode. It returns zero if the specified unfolding is not
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/// possible.
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virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
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bool UnfoldLoad, bool UnfoldStore) const {
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return 0;
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}
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/// BlockHasNoFallThrough - Return true if the specified block does not
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/// fall-through into its successor block. This is primarily used when a
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/// branch is unanalyzable. It is useful for things like unconditional
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/// indirect branches (jump tables).
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virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
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return false;
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}
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/// ReverseBranchCondition - Reverses the branch condition of the specified
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/// condition list, returning false on success and true if it cannot be
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/// reversed.
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virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
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return true;
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}
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/// insertNoop - Insert a noop into the instruction stream at the specified
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/// point.
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virtual void insertNoop(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const {
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assert(0 && "Target didn't implement insertNoop!");
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abort();
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}
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/// isPredicated - Returns true if the instruction is already predicated.
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///
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virtual bool isPredicated(const MachineInstr *MI) const {
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return false;
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}
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/// isUnpredicatedTerminator - Returns true if the instruction is a
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/// terminator instruction that has not been predicated.
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virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
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/// PredicateInstruction - Convert the instruction into a predicated
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/// instruction. It returns true if the operation was successful.
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virtual
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bool PredicateInstruction(MachineInstr *MI,
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const std::vector<MachineOperand> &Pred) const = 0;
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/// SubsumesPredicate - Returns true if the first specified predicate
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/// subsumes the second, e.g. GE subsumes GT.
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virtual
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bool SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
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const std::vector<MachineOperand> &Pred2) const {
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return false;
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}
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/// DefinesPredicate - If the specified instruction defines any predicate
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/// or condition code register(s) used for predication, returns true as well
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/// as the definition predicate(s) by reference.
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virtual bool DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const {
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return false;
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}
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/// getPointerRegClass - Returns a TargetRegisterClass used for pointer
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/// values.
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virtual const TargetRegisterClass *getPointerRegClass() const {
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assert(0 && "Target didn't implement getPointerRegClass!");
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abort();
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return 0; // Must return a value in order to compile with VS 2005
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}
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};
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/// TargetInstrInfoImpl - This is the default implementation of
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/// TargetInstrInfo, which just provides a couple of default implementations
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/// for various methods. This separated out because it is implemented in
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/// libcodegen, not in libtarget.
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class TargetInstrInfoImpl : public TargetInstrInfo {
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protected:
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TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
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: TargetInstrInfo(desc, NumOpcodes) {}
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public:
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virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
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virtual bool CommuteChangesDestination(MachineInstr *MI,
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unsigned &OpIdx) const;
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virtual bool PredicateInstruction(MachineInstr *MI,
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const std::vector<MachineOperand> &Pred) const;
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};
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} // End llvm namespace
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#endif
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