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Update file comment to contain a bunch of the overview mapping-info documentation previously buried within the file. Remove some unnecessary include/using stmts. Rename pass to MappingInfoCollector. Rewrite a lot of it so it doesn't use global instance variables and so it outputs into MappingInfo objects and then dumps those out, instead of going straight to an assembly file. Change name of factory to getMappingInfoCollector. Fold prologue & epilogue writers into MappingInfo methods. lib/Target/Sparc/FInfo.cpp: Correct file comment to reflect above change lib/Target/Sparc/Sparc.cpp: Change name of factory to getMappingInfoCollector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6617 91177308-0d34-0410-b5e6-96231b3b80d8
243 lines
8.7 KiB
C++
243 lines
8.7 KiB
C++
//===-- Sparc.cpp - General implementation file for the Sparc Target ------===//
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//
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// This file contains the code for the Sparc Target that does not fit in any of
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// the other files in this directory.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcInternals.h"
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#include "llvm/Target/TargetMachineImpls.h"
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#include "llvm/Function.h"
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#include "llvm/PassManager.h"
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#include "llvm/Transforms/Scalar.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionInfo.h"
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#include "llvm/CodeGen/PreSelection.h"
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#include "llvm/CodeGen/StackSlots.h"
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#include "llvm/CodeGen/PeepholeOpts.h"
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#include "llvm/CodeGen/InstrSelection.h"
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#include "llvm/CodeGen/InstrScheduling.h"
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#include "llvm/CodeGen/RegisterAllocation.h"
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#include "llvm/CodeGen/MachineCodeForInstruction.h"
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#include "llvm/Reoptimizer/Mapping/MappingInfo.h"
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#include "llvm/Reoptimizer/Mapping/FInfo.h"
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#include "Support/CommandLine.h"
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using std::cerr;
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static const unsigned ImplicitRegUseList[] = { 0 }; /* not used yet */
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// Build the MachineInstruction Description Array...
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const TargetInstrDescriptor SparcMachineInstrDesc[] = {
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#define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
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NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
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{ OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
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NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS, 0, \
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ImplicitRegUseList, ImplicitRegUseList },
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#include "SparcInstr.def"
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};
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//---------------------------------------------------------------------------
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// Command line options to control choice of code generation passes.
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//---------------------------------------------------------------------------
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static cl::opt<bool> DisablePreSelect("nopreselect",
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cl::desc("Disable preselection pass"));
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static cl::opt<bool> DisableSched("nosched",
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cl::desc("Disable local scheduling pass"));
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static cl::opt<bool> DisablePeephole("nopeephole",
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cl::desc("Disable peephole optimization pass"));
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//----------------------------------------------------------------------------
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// allocateSparcTargetMachine - Allocate and return a subclass of TargetMachine
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// that implements the Sparc backend. (the llvm/CodeGen/Sparc.h interface)
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//----------------------------------------------------------------------------
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TargetMachine *allocateSparcTargetMachine(unsigned Configuration) {
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return new UltraSparc();
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}
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//---------------------------------------------------------------------------
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// class UltraSparcFrameInfo
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//
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// Interface to stack frame layout info for the UltraSPARC.
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// Starting offsets for each area of the stack frame are aligned at
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// a multiple of getStackFrameSizeAlignment().
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//---------------------------------------------------------------------------
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int
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UltraSparcFrameInfo::getFirstAutomaticVarOffset(MachineFunction& ,
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bool& pos) const
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{
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pos = false; // static stack area grows downwards
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return StaticAreaOffsetFromFP;
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}
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int
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UltraSparcFrameInfo::getRegSpillAreaOffset(MachineFunction& mcInfo,
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bool& pos) const
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{
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// ensure no more auto vars are added
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mcInfo.getInfo()->freezeAutomaticVarsArea();
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pos = false; // static stack area grows downwards
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unsigned autoVarsSize = mcInfo.getInfo()->getAutomaticVarsSize();
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return StaticAreaOffsetFromFP - autoVarsSize;
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}
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int
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UltraSparcFrameInfo::getTmpAreaOffset(MachineFunction& mcInfo,
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bool& pos) const
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{
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MachineFunctionInfo *MFI = mcInfo.getInfo();
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MFI->freezeAutomaticVarsArea(); // ensure no more auto vars are added
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MFI->freezeSpillsArea(); // ensure no more spill slots are added
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pos = false; // static stack area grows downwards
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unsigned autoVarsSize = MFI->getAutomaticVarsSize();
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unsigned spillAreaSize = MFI->getRegSpillsSize();
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int offset = autoVarsSize + spillAreaSize;
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return StaticAreaOffsetFromFP - offset;
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}
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int
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UltraSparcFrameInfo::getDynamicAreaOffset(MachineFunction& mcInfo,
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bool& pos) const
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{
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// Dynamic stack area grows downwards starting at top of opt-args area.
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// The opt-args, required-args, and register-save areas are empty except
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// during calls and traps, so they are shifted downwards on each
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// dynamic-size alloca.
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pos = false;
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unsigned optArgsSize = mcInfo.getInfo()->getMaxOptionalArgsSize();
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if (int extra = optArgsSize % getStackFrameSizeAlignment())
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optArgsSize += (getStackFrameSizeAlignment() - extra);
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int offset = optArgsSize + FirstOptionalOutgoingArgOffsetFromSP;
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assert((offset - OFFSET) % getStackFrameSizeAlignment() == 0);
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return offset;
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}
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//---------------------------------------------------------------------------
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// class UltraSparcMachine
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//
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// Purpose:
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// Primary interface to machine description for the UltraSPARC.
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// Primarily just initializes machine-dependent parameters in
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// class TargetMachine, and creates machine-dependent subclasses
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// for classes such as TargetInstrInfo.
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//
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//---------------------------------------------------------------------------
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UltraSparc::UltraSparc()
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: TargetMachine("UltraSparc-Native", false),
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schedInfo(*this),
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regInfo(*this),
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frameInfo(*this),
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cacheInfo(*this),
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optInfo(*this) {
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}
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// addPassesToEmitAssembly - This method controls the entire code generation
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// process for the ultra sparc.
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//
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bool UltraSparc::addPassesToEmitAssembly(PassManager &PM, std::ostream &Out)
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{
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// FIXME: implement the switch instruction in the instruction selector.
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PM.add(createLowerSwitchPass());
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// Construct and initialize the MachineFunction object for this fn.
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PM.add(createMachineCodeConstructionPass(*this));
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//Insert empty stackslots in the stack frame of each function
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//so %fp+offset-8 and %fp+offset-16 are empty slots now!
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PM.add(createStackSlotsPass(*this));
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// Specialize LLVM code for this target machine and then
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// run basic dataflow optimizations on LLVM code.
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if (!DisablePreSelect) {
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PM.add(createPreSelectionPass(*this));
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PM.add(createReassociatePass());
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PM.add(createLICMPass());
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PM.add(createGCSEPass());
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}
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PM.add(createInstructionSelectionPass(*this));
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if (!DisableSched)
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PM.add(createInstructionSchedulingWithSSAPass(*this));
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PM.add(getRegisterAllocator(*this));
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PM.add(getPrologEpilogInsertionPass());
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if (!DisablePeephole)
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PM.add(createPeepholeOptsPass(*this));
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PM.add(getMappingInfoCollector(Out));
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// Output assembly language to the .s file. Assembly emission is split into
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// two parts: Function output and Global value output. This is because
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// function output is pipelined with all of the rest of code generation stuff,
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// allowing machine code representations for functions to be free'd after the
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// function has been emitted.
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//
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PM.add(getFunctionAsmPrinterPass(Out));
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PM.add(createMachineCodeDestructionPass()); // Free stuff no longer needed
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// Emit Module level assembly after all of the functions have been processed.
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PM.add(getModuleAsmPrinterPass(Out));
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// Emit bytecode to the assembly file into its special section next
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PM.add(getEmitBytecodeToAsmPass(Out));
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PM.add(getFunctionInfo(Out));
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return false;
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}
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// addPassesToJITCompile - This method controls the JIT method of code
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// generation for the UltraSparc.
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//
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bool UltraSparc::addPassesToJITCompile(PassManager &PM) {
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// FIXME: implement the switch instruction in the instruction selector.
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PM.add(createLowerSwitchPass());
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// Construct and initialize the MachineFunction object for this fn.
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PM.add(createMachineCodeConstructionPass(*this));
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//Insert empty stackslots in the stack frame of each function
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//so %fp+offset-8 and %fp+offset-16 are empty slots now!
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PM.add(createStackSlotsPass(*this));
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// Specialize LLVM code for this target machine and then
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// run basic dataflow optimizations on LLVM code.
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#if 0
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if (!DisablePreSelect) {
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PM.add(createPreSelectionPass(*this));
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PM.add(createReassociatePass());
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PM.add(createLICMPass());
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PM.add(createGCSEPass());
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}
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#endif
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PM.add(createInstructionSelectionPass(*this));
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#if 0
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if (!DisableSched)
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PM.add(createInstructionSchedulingWithSSAPass(*this));
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#endif
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// new pass: convert Value* in MachineOperand to an unsigned register
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// this brings it in line with what the X86 JIT's RegisterAllocator expects
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//PM.add(createAddRegNumToValuesPass());
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PM.add(getRegisterAllocator(*this));
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PM.add(getPrologEpilogInsertionPass());
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#if 0
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if (!DisablePeephole)
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PM.add(createPeepholeOptsPass(*this));
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#endif
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return false; // success!
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}
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