Tom Stellard 334ebf33ea R600/SI: Make SIInstrInfo::isOperandLegal() more strict ... A register operand that has a common sub-class with its instruction's defined register class is not always legal. For example, SReg_32 and M0Reg both have a common sub-class, but we can't use an SReg_32 in instructions that expect a M0Reg. This prevents the llvm.SI.sendmsg.ll test from failing when the fold operand pass is added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222368 91177308-0d34-0410-b5e6-96231b3b80d8		2014-11-19 16:58:49 +00:00
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AArch64	[AArch64] Enable SeparateConstOffsetFromGEP, EarlyCSE and LICM passes on AArch64 backend.	2014-11-19 06:39:53 +00:00
ARM	Fix ARM triple parsing	2014-11-17 14:08:57 +00:00
CPP
Generic
Hexagon
Inputs
Mips	[mips][microMIPS] Implement CodeGen support for 16-bit instruction ADDIUR2.	2014-11-19 13:23:58 +00:00
MSP430
NVPTX
PowerPC
R600	R600/SI: Make SIInstrInfo::isOperandLegal() more strict	2014-11-19 16:58:49 +00:00
SPARC
SystemZ
Thumb	[Thumb1] Re-write emitThumbRegPlusImmediate	2014-11-17 11:18:10 +00:00
Thumb2
X86	[X86][SSE] pslldq/psrldq byte shifts/rotation for SSE2	2014-11-19 10:06:49 +00:00
XCore