Adam Nemet 6ae2941874 [X86] AVX512: Add disassembler support for compressed displacement ... There are two parts here. First is to modify tablegen to adjust the encoding type ENCODING_RM with the scaling factor. The second is to use the new encoding types to compute the correct displacement in the decoder. Fixes <rdar://problem/17608489> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213281 91177308-0d34-0410-b5e6-96231b3b80d8		2014-07-17 17:04:56 +00:00
..
avx-512.txt	[X86] AVX512: Add disassembler support for compressed displacement	2014-07-17 17:04:56 +00:00
fp-stack.txt	Add two fp test cases I missed in my previous commit.	2013-12-31 23:15:19 +00:00
hex-immediates.txt	llvm-mc: Add option for prefering hex format disassembly.	2014-06-11 20:26:40 +00:00
intel-syntax-32.txt
intel-syntax.txt
invalid-cmp-imm.txt
invalid-VEX-vvvv.txt
lit.local.cfg	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
marked-up.txt
missing-sib.txt	Test case for r204305.	2014-03-20 06:45:10 +00:00
moffs.txt	llvm-mc: Add option for prefering hex format disassembly.	2014-06-11 20:26:40 +00:00
padlock.txt	Remove A6/A7 opcode maps. They can all be handled with a TB map, opcode of 0xa6/0xa7, and adding MRM_C0/MRM_E0 forms. Removes 376K from the disassembler tables.	2014-02-19 05:34:21 +00:00
prefixes.txt	X86Disassembler - fixed a bug in immediate print	2014-04-23 07:21:04 +00:00
simple-tests.txt	Remove need for MODIFIER_OPCODE in the disassembler tables. AddRegFrms are really more like OrRegFrm so we don't need a difference since we can just mask bits.	2014-01-01 15:29:32 +00:00
truncated-input.txt
x86-16.txt	[x86] Fix 16-bit disassembly of JCXZ/JECXZ	2014-01-20 12:02:48 +00:00
x86-32.txt	[X86] Add disassembler support for the 0x0f 0x7f form of movq %mm, %mm.	2014-04-17 06:33:45 +00:00
x86-64.txt	Fix diassembler handling of rex.b when mod=00/01/10 and bbb=101. Mod=00 should ignore the base register entirely. Mod=01/10 should treat this as R13 plus displacment. Fixes PR18860.	2014-02-17 10:03:43 +00:00