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335dd0d1a6
Previously, when spilling 64-bit paired registers, an LDMIA with both a FrameIndex and an offset was produced. This kind of instruction shouldn't exist, and the extra operand was being confused with the predicate, causing aborts later on. This removes the invalid 0-offset from the instruction being produced. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179956 91177308-0d34-0410-b5e6-96231b3b80d8
37 lines
1.6 KiB
LLVM
37 lines
1.6 KiB
LLVM
; RUN: llc -mtriple=armv7-none-linux-gnueabi < %s | FileCheck %s
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define void @foo(i64* %addr) {
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%val1 = tail call i64 asm sideeffect "ldrd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
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%val2 = tail call i64 asm sideeffect "ldrd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
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%val3 = tail call i64 asm sideeffect "ldrd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
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%val4 = tail call i64 asm sideeffect "ldrd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
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%val5 = tail call i64 asm sideeffect "ldrd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
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%val6 = tail call i64 asm sideeffect "ldrd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
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%val7 = tail call i64 asm sideeffect "ldrd $0, ${0:H}, [r0]", "=&r,r"(i64* %addr)
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; Key point is that enough 64-bit paired GPR values are live that
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; one of them has to be spilled. This used to cause an abort because
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; an LDMIA was created with both a FrameIndex and an offset, which
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; is not allowed.
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; We also want to ensure the register scavenger is working (i.e. an
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; offset from sp can be generated), so we need two spills.
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; CHECK: add [[ADDRREG:[a-z0-9]+]], sp, #{{[0-9]+}}
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; CHECK: stm [[ADDRREG]], {r{{[0-9]+}}, r{{[0-9]+}}}
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; CHECK: stm sp, {r{{[0-9]+}}, r{{[0-9]+}}}
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; In principle LLVM may have to recalculate the offset. At the moment
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; it reuses the original though.
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; CHECK: ldm [[ADDRREG]], {r{{[0-9]+}}, r{{[0-9]+}}}
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; CHECK: ldm sp, {r{{[0-9]+}}, r{{[0-9]+}}}
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store volatile i64 %val1, i64* %addr
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store volatile i64 %val2, i64* %addr
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store volatile i64 %val3, i64* %addr
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store volatile i64 %val4, i64* %addr
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store volatile i64 %val5, i64* %addr
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store volatile i64 %val6, i64* %addr
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store volatile i64 %val7, i64* %addr
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ret void
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}
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