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A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
133 lines
3.6 KiB
C++
133 lines
3.6 KiB
C++
//===-- AMDGPUInstPrinter.cpp - AMDGPU MC Inst -> ASM ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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// \file
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//===----------------------------------------------------------------------===//
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#include "AMDGPUInstPrinter.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "llvm/MC/MCInst.h"
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using namespace llvm;
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void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
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StringRef Annot) {
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printInstruction(MI, OS);
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printAnnotation(OS, Annot);
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}
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void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isReg()) {
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switch (Op.getReg()) {
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// This is the default predicate state, so we don't need to print it.
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case AMDGPU::PRED_SEL_OFF: break;
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default: O << getRegisterName(Op.getReg()); break;
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}
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} else if (Op.isImm()) {
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O << Op.getImm();
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} else if (Op.isFPImm()) {
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O << Op.getFPImm();
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} else {
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assert(!"unknown operand type in printOperand");
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}
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}
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void AMDGPUInstPrinter::printMemOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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printOperand(MI, OpNo, O);
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O << ", ";
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printOperand(MI, OpNo + 1, O);
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}
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void AMDGPUInstPrinter::printIfSet(const MCInst *MI, unsigned OpNo,
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raw_ostream &O, StringRef Asm) {
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const MCOperand &Op = MI->getOperand(OpNo);
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assert(Op.isImm());
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if (Op.getImm() == 1) {
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O << Asm;
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}
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}
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void AMDGPUInstPrinter::printAbs(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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printIfSet(MI, OpNo, O, "|");
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}
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void AMDGPUInstPrinter::printClamp(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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printIfSet(MI, OpNo, O, "_SAT");
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}
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void AMDGPUInstPrinter::printLiteral(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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union Literal {
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float f;
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int32_t i;
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} L;
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L.i = MI->getOperand(OpNo).getImm();
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O << L.i << "(" << L.f << ")";
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}
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void AMDGPUInstPrinter::printLast(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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printIfSet(MI, OpNo, O, " *");
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}
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void AMDGPUInstPrinter::printNeg(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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printIfSet(MI, OpNo, O, "-");
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}
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void AMDGPUInstPrinter::printOMOD(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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switch (MI->getOperand(OpNo).getImm()) {
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default: break;
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case 1:
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O << " * 2.0";
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break;
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case 2:
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O << " * 4.0";
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break;
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case 3:
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O << " / 2.0";
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break;
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}
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}
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void AMDGPUInstPrinter::printRel(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.getImm() != 0) {
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O << " + " << Op.getImm();
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}
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}
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void AMDGPUInstPrinter::printUpdateExecMask(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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printIfSet(MI, OpNo, O, "ExecMask,");
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}
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void AMDGPUInstPrinter::printUpdatePred(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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printIfSet(MI, OpNo, O, "Pred,");
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}
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void AMDGPUInstPrinter::printWrite(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.getImm() == 0) {
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O << " (MASKED)";
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}
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}
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#include "AMDGPUGenAsmWriter.inc"
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