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f98f2ce29e
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
63 lines
2.6 KiB
C++
63 lines
2.6 KiB
C++
//===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief SI DAG Lowering interface definition
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//
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//===----------------------------------------------------------------------===//
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#ifndef SIISELLOWERING_H
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#define SIISELLOWERING_H
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#include "AMDGPUISelLowering.h"
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#include "SIInstrInfo.h"
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namespace llvm {
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class SITargetLowering : public AMDGPUTargetLowering {
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const SIInstrInfo * TII;
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/// Memory reads and writes are syncronized using the S_WAITCNT instruction.
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/// This function takes the most conservative approach and inserts an
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/// S_WAITCNT instruction after every read and write.
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void AppendS_WAITCNT(MachineInstr *MI, MachineBasicBlock &BB,
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MachineBasicBlock::iterator I) const;
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void LowerMOV_IMM(MachineInstr *MI, MachineBasicBlock &BB,
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MachineBasicBlock::iterator I, unsigned Opocde) const;
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void LowerSI_INTERP(MachineInstr *MI, MachineBasicBlock &BB,
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MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
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void LowerSI_INTERP_CONST(MachineInstr *MI, MachineBasicBlock &BB,
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MachineBasicBlock::iterator I, MachineRegisterInfo &MRI) const;
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void LowerSI_KIL(MachineInstr *MI, MachineBasicBlock &BB,
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MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
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void LowerSI_WQM(MachineInstr *MI, MachineBasicBlock &BB,
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MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
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void LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB,
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MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
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SDValue Loweri1ContextSwitch(SDValue Op, SelectionDAG &DAG,
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unsigned VCCNode) const;
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SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
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public:
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SITargetLowering(TargetMachine &tm);
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virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr * MI,
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MachineBasicBlock * BB) const;
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virtual EVT getSetCCResultType(EVT VT) const;
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virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
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virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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virtual const char* getTargetNodeName(unsigned Opcode) const;
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};
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} // End namespace llvm
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#endif //SIISELLOWERING_H
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