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5bafff36c7
This is still a work in progress but most of the NEON instruction set is supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73919 91177308-0d34-0410-b5e6-96231b3b80d8
34 lines
1.1 KiB
LLVM
34 lines
1.1 KiB
LLVM
; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
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; RUN: grep {vrecpe\\.u32} %t | count 2
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; RUN: grep {vrecpe\\.f32} %t | count 2
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define <2 x i32> @vrecpei32(<2 x i32>* %A) nounwind {
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%tmp1 = load <2 x i32>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32> %tmp1)
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ret <2 x i32> %tmp2
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}
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define <4 x i32> @vrecpeQi32(<4 x i32>* %A) nounwind {
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%tmp1 = load <4 x i32>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32> %tmp1)
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ret <4 x i32> %tmp2
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}
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define <2 x float> @vrecpef32(<2 x float>* %A) nounwind {
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%tmp1 = load <2 x float>* %A
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%tmp2 = call <2 x float> @llvm.arm.neon.vrecpef.v2f32(<2 x float> %tmp1)
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ret <2 x float> %tmp2
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}
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define <4 x float> @vrecpeQf32(<4 x float>* %A) nounwind {
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%tmp1 = load <4 x float>* %A
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%tmp2 = call <4 x float> @llvm.arm.neon.vrecpef.v4f32(<4 x float> %tmp1)
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ret <4 x float> %tmp2
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}
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declare <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32>) nounwind readnone
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declare <2 x float> @llvm.arm.neon.vrecpef.v2f32(<2 x float>) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vrecpef.v4f32(<4 x float>) nounwind readnone
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