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https://github.com/c64scene-ar/llvm-6502.git
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d410eaba04
test suite failures. The failures occur at each stage, and only get worse, so I'm reverting all of them. Please resubmit these patches, one at a time, after verifying that the regression test suite passes. Never submit a patch without running the regression test suite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155372 91177308-0d34-0410-b5e6-96231b3b80d8
316 lines
11 KiB
C++
316 lines
11 KiB
C++
//===-- HexagonRegisterInfo.cpp - Hexagon Register Information ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Hexagon implementation of the TargetRegisterInfo
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// class.
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//
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//===----------------------------------------------------------------------===//
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#include "HexagonRegisterInfo.h"
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#include "Hexagon.h"
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#include "HexagonSubtarget.h"
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#include "HexagonTargetMachine.h"
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#include "HexagonMachineFunctionInfo.h"
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#include "llvm/Function.h"
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#include "llvm/Type.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/MC/MachineLocation.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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HexagonRegisterInfo::HexagonRegisterInfo(HexagonSubtarget &st,
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const HexagonInstrInfo &tii)
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: HexagonGenRegisterInfo(Hexagon::R31),
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Subtarget(st),
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TII(tii) {
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}
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const uint16_t* HexagonRegisterInfo::getCalleeSavedRegs(const MachineFunction
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*MF)
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const {
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static const uint16_t CalleeSavedRegsV2[] = {
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Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
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};
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static const uint16_t CalleeSavedRegsV3[] = {
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Hexagon::R16, Hexagon::R17, Hexagon::R18, Hexagon::R19,
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Hexagon::R20, Hexagon::R21, Hexagon::R22, Hexagon::R23,
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Hexagon::R24, Hexagon::R25, Hexagon::R26, Hexagon::R27, 0
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};
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switch(Subtarget.getHexagonArchVersion()) {
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case HexagonSubtarget::V1:
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break;
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case HexagonSubtarget::V2:
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return CalleeSavedRegsV2;
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case HexagonSubtarget::V3:
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case HexagonSubtarget::V4:
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return CalleeSavedRegsV3;
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}
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llvm_unreachable("Callee saved registers requested for unknown architecture "
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"version");
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}
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BitVector HexagonRegisterInfo::getReservedRegs(const MachineFunction &MF)
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const {
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BitVector Reserved(getNumRegs());
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Reserved.set(HEXAGON_RESERVED_REG_1);
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Reserved.set(HEXAGON_RESERVED_REG_2);
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Reserved.set(Hexagon::R29);
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Reserved.set(Hexagon::R30);
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Reserved.set(Hexagon::R31);
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Reserved.set(Hexagon::D14);
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Reserved.set(Hexagon::D15);
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Reserved.set(Hexagon::LC0);
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Reserved.set(Hexagon::LC1);
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Reserved.set(Hexagon::SA0);
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Reserved.set(Hexagon::SA1);
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return Reserved;
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}
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const TargetRegisterClass* const*
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HexagonRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
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static const TargetRegisterClass * const CalleeSavedRegClassesV2[] = {
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&Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
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&Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
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};
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static const TargetRegisterClass * const CalleeSavedRegClassesV3[] = {
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&Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
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&Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
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&Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
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&Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
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&Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
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&Hexagon::IntRegsRegClass, &Hexagon::IntRegsRegClass,
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};
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switch(Subtarget.getHexagonArchVersion()) {
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case HexagonSubtarget::V1:
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break;
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case HexagonSubtarget::V2:
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return CalleeSavedRegClassesV2;
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case HexagonSubtarget::V3:
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case HexagonSubtarget::V4:
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return CalleeSavedRegClassesV3;
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}
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llvm_unreachable("Callee saved register classes requested for unknown "
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"architecture version");
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}
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void HexagonRegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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MachineInstr &MI = *I;
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if (MI.getOpcode() == Hexagon::ADJCALLSTACKDOWN) {
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// Hexagon_TODO: add code
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} else if (MI.getOpcode() == Hexagon::ADJCALLSTACKUP) {
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// Hexagon_TODO: add code
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} else {
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llvm_unreachable("Cannot handle this call frame pseudo instruction");
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}
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MBB.erase(I);
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}
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void HexagonRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, RegScavenger *RS) const {
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//
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// Hexagon_TODO: Do we need to enforce this for Hexagon?
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assert(SPAdj == 0 && "Unexpected");
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unsigned i = 0;
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MachineInstr &MI = *II;
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while (!MI.getOperand(i).isFI()) {
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++i;
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assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
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}
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int FrameIndex = MI.getOperand(i).getIndex();
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// Addressable stack objects are accessed using neg. offsets from %fp.
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MachineFunction &MF = *MI.getParent()->getParent();
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int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
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MachineFrameInfo &MFI = *MF.getFrameInfo();
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unsigned FrameReg = getFrameRegister(MF);
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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if (!TFI->hasFP(MF)) {
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// We will not reserve space on the stack for the lr and fp registers.
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Offset -= 2 * Hexagon_WordSize;
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}
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const unsigned FrameSize = MFI.getStackSize();
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if (!MFI.hasVarSizedObjects() &&
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TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) &&
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!TII.isSpillPredRegOp(&MI)) {
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// Replace frame index with a stack pointer reference.
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MI.getOperand(i).ChangeToRegister(getStackRegister(), false, false, true);
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MI.getOperand(i+1).ChangeToImmediate(FrameSize+Offset);
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} else {
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// Replace frame index with a frame pointer reference.
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if (!TII.isValidOffset(MI.getOpcode(), Offset)) {
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// If the offset overflows, then correct it.
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//
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// For loads, we do not need a reserved register
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// r0 = memw(r30 + #10000) to:
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//
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// r0 = add(r30, #10000)
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// r0 = memw(r0)
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if ( (MI.getOpcode() == Hexagon::LDriw) ||
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(MI.getOpcode() == Hexagon::LDrid) ||
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(MI.getOpcode() == Hexagon::LDrih) ||
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(MI.getOpcode() == Hexagon::LDriuh) ||
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(MI.getOpcode() == Hexagon::LDrib) ||
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(MI.getOpcode() == Hexagon::LDriub) ) {
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unsigned dstReg = (MI.getOpcode() == Hexagon::LDrid) ?
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*getSubRegisters(MI.getOperand(0).getReg()) :
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MI.getOperand(0).getReg();
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// Check if offset can fit in addi.
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if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) {
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BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
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TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset);
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BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
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TII.get(Hexagon::ADD_rr),
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dstReg).addReg(FrameReg).addReg(dstReg);
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} else {
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BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
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TII.get(Hexagon::ADD_ri),
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dstReg).addReg(FrameReg).addImm(Offset);
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}
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MI.getOperand(i).ChangeToRegister(dstReg, false, false, true);
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MI.getOperand(i+1).ChangeToImmediate(0);
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} else if ((MI.getOpcode() == Hexagon::STriw) ||
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(MI.getOpcode() == Hexagon::STrid) ||
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(MI.getOpcode() == Hexagon::STrih) ||
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(MI.getOpcode() == Hexagon::STrib)) {
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// For stores, we need a reserved register. Change
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// memw(r30 + #10000) = r0 to:
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//
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// rs = add(r30, #10000);
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// memw(rs) = r0
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unsigned resReg = HEXAGON_RESERVED_REG_1;
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// Check if offset can fit in addi.
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if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) {
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BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
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TII.get(Hexagon::CONST32_Int_Real), resReg).addImm(Offset);
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BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
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TII.get(Hexagon::ADD_rr),
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resReg).addReg(FrameReg).addReg(resReg);
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} else {
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BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
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TII.get(Hexagon::ADD_ri),
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resReg).addReg(FrameReg).addImm(Offset);
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}
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MI.getOperand(i).ChangeToRegister(resReg, false, false, true);
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MI.getOperand(i+1).ChangeToImmediate(0);
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} else if (TII.isMemOp(&MI)) {
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unsigned resReg = HEXAGON_RESERVED_REG_1;
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if (!MFI.hasVarSizedObjects() &&
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TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset))) {
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MI.getOperand(i).ChangeToRegister(getStackRegister(), false, false,
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true);
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MI.getOperand(i+1).ChangeToImmediate(FrameSize+Offset);
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} else if (!TII.isValidOffset(Hexagon::ADD_ri, Offset)) {
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BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
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TII.get(Hexagon::CONST32_Int_Real), resReg).addImm(Offset);
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BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
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TII.get(Hexagon::ADD_rr),
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resReg).addReg(FrameReg).addReg(resReg);
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MI.getOperand(i).ChangeToRegister(resReg, false, false, true);
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MI.getOperand(i+1).ChangeToImmediate(0);
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} else {
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BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
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TII.get(Hexagon::ADD_ri),
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resReg).addReg(FrameReg).addImm(Offset);
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MI.getOperand(i).ChangeToRegister(resReg, false, false, true);
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MI.getOperand(i+1).ChangeToImmediate(0);
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}
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} else {
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unsigned dstReg = MI.getOperand(0).getReg();
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BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
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TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset);
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BuildMI(*MI.getParent(), II, MI.getDebugLoc(),
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TII.get(Hexagon::ADD_rr),
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dstReg).addReg(FrameReg).addReg(dstReg);
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// Can we delete MI??? r2 = add (r2, #0).
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MI.getOperand(i).ChangeToRegister(dstReg, false, false, true);
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MI.getOperand(i+1).ChangeToImmediate(0);
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}
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} else {
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// If the offset is small enough to fit in the immediate field, directly
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// encode it.
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MI.getOperand(i).ChangeToRegister(FrameReg, false);
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MI.getOperand(i+1).ChangeToImmediate(Offset);
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}
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}
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}
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unsigned HexagonRegisterInfo::getRARegister() const {
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return Hexagon::R31;
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}
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unsigned HexagonRegisterInfo::getFrameRegister(const MachineFunction
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&MF) const {
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const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
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if (TFI->hasFP(MF)) {
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return Hexagon::R30;
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}
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return Hexagon::R29;
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}
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unsigned HexagonRegisterInfo::getFrameRegister() const {
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return Hexagon::R30;
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}
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unsigned HexagonRegisterInfo::getStackRegister() const {
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return Hexagon::R29;
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}
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void HexagonRegisterInfo::getInitialFrameState(std::vector<MachineMove>
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&Moves) const
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{
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// VirtualFP = (R30 + #0).
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unsigned FPReg = getFrameRegister();
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MachineLocation Dst(MachineLocation::VirtualFP);
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MachineLocation Src(FPReg, 0);
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Moves.push_back(MachineMove(0, Dst, Src));
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}
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unsigned HexagonRegisterInfo::getEHExceptionRegister() const {
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llvm_unreachable("What is the exception register");
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}
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unsigned HexagonRegisterInfo::getEHHandlerRegister() const {
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llvm_unreachable("What is the exception handler register");
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}
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#define GET_REGINFO_TARGET_DESC
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#include "HexagonGenRegisterInfo.inc"
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