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6a8c7bf8e7
on X86 Atom. Some of our tests failed because the tail merging part of the BranchFolding pass was creating new basic blocks which did not contain live-in information. When the anti-dependency code in the Post-RA scheduler ran, it would sometimes rename the register containing the function return value because the fact that the return value was live-in to the subsequent block had been lost. To fix this, it is necessary to run the RegisterScavenging code in the BranchFolding pass. This patch makes sure that the register scavenging code is invoked in the X86 subtarget only when post-RA scheduling is being done. Post RA scheduling in the X86 subtarget is only done for Atom. This patch adds a new function to the TargetRegisterClass to control whether or not live-ins should be preserved during branch folding. This is necessary in order for the anti-dependency optimizations done during the PostRASchedulerList pass to work properly when doing Post-RA scheduling for the X86 in general and for the Intel Atom in particular. The patch adds and invokes the new function trackLivenessAfterRegAlloc() instead of using the existing requiresRegisterScavenging(). It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of requiresRegisterScavenging(). It changes the all the targets that implemented requiresRegisterScavenging() to also implement trackLivenessAfterRegAlloc(). It adds an assertion in the Post RA scheduler to make sure that post RA liveness information is available when it is needed. It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order to avoid running into the added assertion. Finally, this patch restores the use of anti-dependency checking (which was turned off temporarily for the 3.1 release) for Intel Atom in the Post RA scheduler. Patch by Andy Zhang! Thanks to Jakob and Anton for their reviews. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155395 91177308-0d34-0410-b5e6-96231b3b80d8
95 lines
3.1 KiB
C++
95 lines
3.1 KiB
C++
//==- HexagonRegisterInfo.h - Hexagon Register Information Impl --*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Hexagon implementation of the TargetRegisterInfo
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// class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef HexagonREGISTERINFO_H
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#define HexagonREGISTERINFO_H
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/MC/MachineLocation.h"
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#define GET_REGINFO_HEADER
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#include "HexagonGenRegisterInfo.inc"
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//
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// We try not to hard code the reserved registers in our code,
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// so the following two macros were defined. However, there
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// are still a few places that R11 and R10 are hard wired.
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// See below. If, in the future, we decided to change the reserved
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// register. Don't forget changing the following places.
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//
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// 1. the "Defs" set of STriw_pred in HexagonInstrInfo.td
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// 2. the "Defs" set of LDri_pred in HexagonInstrInfo.td
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// 3. the definition of "IntRegs" in HexagonRegisterInfo.td
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// 4. the definition of "DoubleRegs" in HexagonRegisterInfo.td
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//
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#define HEXAGON_RESERVED_REG_1 Hexagon::R10
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#define HEXAGON_RESERVED_REG_2 Hexagon::R11
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namespace llvm {
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class HexagonSubtarget;
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class HexagonInstrInfo;
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class Type;
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struct HexagonRegisterInfo : public HexagonGenRegisterInfo {
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HexagonSubtarget &Subtarget;
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const HexagonInstrInfo &TII;
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HexagonRegisterInfo(HexagonSubtarget &st, const HexagonInstrInfo &tii);
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/// Code Generation virtual methods...
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const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
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const TargetRegisterClass* const* getCalleeSavedRegClasses(
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const MachineFunction *MF = 0) const;
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BitVector getReservedRegs(const MachineFunction &MF) const;
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void eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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void eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, RegScavenger *RS = NULL) const;
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/// determineFrameLayout - Determine the size of the frame and maximum call
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/// frame size.
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void determineFrameLayout(MachineFunction &MF) const;
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/// requiresRegisterScavenging - returns true since we may need scavenging for
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/// a temporary register when generating hardware loop instructions.
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bool requiresRegisterScavenging(const MachineFunction &MF) const {
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return true;
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}
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bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
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return true;
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}
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// Debug information queries.
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unsigned getRARegister() const;
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unsigned getFrameRegister(const MachineFunction &MF) const;
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unsigned getFrameRegister() const;
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void getInitialFrameState(std::vector<MachineMove> &Moves) const;
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unsigned getStackRegister() const;
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// Exception handling queries.
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unsigned getEHExceptionRegister() const;
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unsigned getEHHandlerRegister() const;
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};
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} // end namespace llvm
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#endif
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