mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-19 19:29:31 +00:00
137f7202c7
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@614 91177308-0d34-0410-b5e6-96231b3b80d8
551 lines
16 KiB
C++
551 lines
16 KiB
C++
#include "llvm/CodeGen/PhyRegAlloc.h"
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//----------------------------------------------------------------------------
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//
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//----------------------------------------------------------------------------
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//----------------------------------------------------------------------------
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// Constructor: Init local composite objects and create register classes.
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//----------------------------------------------------------------------------
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PhyRegAlloc::PhyRegAlloc(const Method *const M,
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const TargetMachine& tm,
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MethodLiveVarInfo *const Lvi)
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: RegClassList(),
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Meth(M), TM(tm), LVI(Lvi), LRI(M, tm, RegClassList),
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MRI( tm.getRegInfo() ),
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NumOfRegClasses(MRI.getNumOfRegClasses()),
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CallInstrList(),
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AddedInstrMap()
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{
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// **TODO: use an actual reserved color list
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ReservedColorListType *RCL = new ReservedColorListType();
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// create each RegisterClass and put in RegClassList
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for( unsigned int rc=0; rc < NumOfRegClasses; rc++)
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RegClassList.push_back( new RegClass(M, MRI.getMachineRegClass(rc), RCL) );
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}
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//----------------------------------------------------------------------------
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// This method initally creates interference graphs (one in each reg class)
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// and IGNodeList (one in each IG). The actual nodes will be pushed later.
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//----------------------------------------------------------------------------
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void PhyRegAlloc::createIGNodeListsAndIGs()
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{
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if(DEBUG_RA ) cout << "Creating LR lists ..." << endl;
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// hash map iterator
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LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
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// hash map end
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LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
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for( ; HMI != HMIEnd ; ++HMI ) {
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LiveRange *L = (*HMI).second; // get the LiveRange
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if( (*HMI).first ) {
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// if the Value * is not null, and LR
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// is not yet written to the IGNodeList
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if( !(L->getUserIGNode()) ) {
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RegClass *const RC = // RegClass of first value in the LR
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//RegClassList [MRI.getRegClassIDOfValue(*(L->begin()))];
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RegClassList[ L->getRegClass()->getID() ];
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RC-> addLRToIG( L ); // add this LR to an IG
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}
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}
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}
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// init RegClassList
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[ rc ]->createInterferenceGraph();
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if( DEBUG_RA)
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cout << "LRLists Created!" << endl;
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}
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//----------------------------------------------------------------------------
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// This method will add all interferences at for a given instruction.
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// Interence occurs only if the LR of Def (Inst or Arg) is of the same reg
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// class as that of live var. The live var passed to this function is the
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// LVset AFTER the instruction
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//----------------------------------------------------------------------------
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void PhyRegAlloc::addInterference(const Value *const Def,
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const LiveVarSet *const LVSet,
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const bool isCallInst) {
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LiveVarSet::const_iterator LIt = LVSet->begin();
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// get the live range of instruction
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const LiveRange *const LROfDef = LRI.getLiveRangeForValue( Def );
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IGNode *const IGNodeOfDef = LROfDef->getUserIGNode();
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assert( IGNodeOfDef );
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RegClass *const RCOfDef = LROfDef->getRegClass();
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// for each live var in live variable set
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for( ; LIt != LVSet->end(); ++LIt) {
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if( DEBUG_RA > 1) {
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cout << "< Def="; printValue(Def);
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cout << ", Lvar="; printValue( *LIt); cout << "> ";
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}
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// get the live range corresponding to live var
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LiveRange *const LROfVar = LRI.getLiveRangeForValue(*LIt );
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// LROfVar can be null if it is a const since a const
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// doesn't have a dominating def - see Assumptions above
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if( LROfVar) {
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if(LROfDef == LROfVar) // do not set interf for same LR
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continue;
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// if 2 reg classes are the same set interference
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if( RCOfDef == LROfVar->getRegClass() ){
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RCOfDef->setInterference( LROfDef, LROfVar);
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}
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//the live range of this var interferes with this call
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if( isCallInst )
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LROfVar->addCallInterference( (const Instruction *const) Def );
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}
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else if(DEBUG_RA > 1) {
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// we will not have LRs for values not explicitly allocated in the
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// instruction stream (e.g., constants)
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cout << " warning: no live range for " ;
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printValue( *LIt); cout << endl; }
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}
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}
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//----------------------------------------------------------------------------
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// This method will walk thru code and create interferences in the IG of
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// each RegClass.
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//----------------------------------------------------------------------------
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void PhyRegAlloc::buildInterferenceGraphs()
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{
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if(DEBUG_RA) cout << "Creating interference graphs ..." << endl;
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Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
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for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
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// get the iterator for machine instructions
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const MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
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MachineCodeForBasicBlock::const_iterator
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MInstIterator = MIVec.begin();
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// iterate over all the machine instructions in BB
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for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
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const MachineInstr *const MInst = *MInstIterator;
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// get the LV set after the instruction
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const LiveVarSet *const LVSetAI =
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LVI->getLiveVarSetAfterMInst(MInst, *BBI);
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const bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
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// iterate over MI operands to find defs
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for( MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done(); ++OpI) {
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if( OpI.isDef() ) {
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// create a new LR iff this operand is a def
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addInterference(*OpI, LVSetAI, isCallInst );
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} //if this is a def
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} // for all operands
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} // for all machine instructions in BB
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// go thru LLVM instructions in the basic block and record all CALL
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// instructions in the CallInstrList
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BasicBlock::const_iterator InstIt = (*BBI)->begin();
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for( ; InstIt != (*BBI)->end() ; ++ InstIt) {
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if( (*InstIt)->getOpcode() == Instruction::Call )
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CallInstrList.push_back( *InstIt );
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}
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} // for all BBs in method
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// add interferences for method arguments. Since there are no explict
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// defs in method for args, we have to add them manually
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addInterferencesForArgs(); // add interference for method args
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if( DEBUG_RA)
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cout << "Interference graphs calculted!" << endl;
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}
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//----------------------------------------------------------------------------
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// This method will add interferences for incoming arguments to a method.
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//----------------------------------------------------------------------------
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void PhyRegAlloc::addInterferencesForArgs()
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{
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// get the InSet of root BB
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const LiveVarSet *const InSet = LVI->getInSetOfBB( Meth->front() );
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// get the argument list
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const Method::ArgumentListType& ArgList = Meth->getArgumentList();
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// get an iterator to arg list
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Method::ArgumentListType::const_iterator ArgIt = ArgList.begin();
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for( ; ArgIt != ArgList.end() ; ++ArgIt) { // for each argument
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addInterference( *ArgIt, InSet, false ); // add interferences between
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// args and LVars at start
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if( DEBUG_RA > 1) {
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cout << " - %% adding interference for argument ";
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printValue( (const Value *) *ArgIt); cout << endl;
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}
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}
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}
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//----------------------------------------------------------------------------
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// This method is called after register allocation is complete to set the
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// allocated reisters in the machine code. This code will add register numbers
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// to MachineOperands that contain a Value.
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//----------------------------------------------------------------------------
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void PhyRegAlloc::updateMachineCode()
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{
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Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
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for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
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// get the iterator for machine instructions
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MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
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MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
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// iterate over all the machine instructions in BB
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for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
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MachineInstr *const MInst = *MInstIterator;
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//for(MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done();++OpI) {
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for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
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MachineOperand& Op = MInst->getOperand(OpNum);
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if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
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Op.getOperandType() == MachineOperand::MO_CCRegister) {
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const Value *const Val = Op.getVRegValue();
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// delete this condition checking later (must assert if Val is null)
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if( !Val ) {
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cout << "Error: NULL Value found in instr." << endl;
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Op.setRegForValue( 10000 ); // an invalid value is set
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continue;
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}
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assert( Val && "Value is NULL");
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const LiveRange *const LR = LRI.getLiveRangeForValue(Val);
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if ( !LR ) {
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if( ! ( (Val->getType())->isLabelType() ||
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(Val->getValueType() == Value::ConstantVal) ) ) {
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cout << "Warning: No LiveRange for: ";
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printValue( Val); cout << endl;
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}
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//assert( LR && "No LR found for Value");
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continue;
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}
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unsigned RCID = (LR->getRegClass())->getID();
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Op.setRegForValue( MRI.getUnifiedRegNum(RCID, LR->getColor()) );
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int RegNum = MRI.getUnifiedRegNum(RCID, LR->getColor());
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}
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}
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}
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}
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}
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//----------------------------------------------------------------------------
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// This method prints the code with registers after register allocation is
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// complete.
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//----------------------------------------------------------------------------
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void PhyRegAlloc::printMachineCode()
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{
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cout << endl << ";************** Method ";
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cout << Meth->getName() << " *****************" << endl;
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Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
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for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
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cout << endl ; printLabel( *BBI); cout << ": ";
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// get the iterator for machine instructions
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MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
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MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
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// iterate over all the machine instructions in BB
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for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
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MachineInstr *const MInst = *MInstIterator;
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cout << endl << "\t";
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cout << TargetInstrDescriptors[MInst->getOpCode()].opCodeString;
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//for(MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done();++OpI) {
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for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
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MachineOperand& Op = MInst->getOperand(OpNum);
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if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
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Op.getOperandType() == MachineOperand::MO_CCRegister ||
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Op.getOperandType() == MachineOperand::MO_MachineRegister ) {
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const int RegNum = (const int) Op.getAllocatedRegNum();
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// ****this code is temporary till NULL Values are fixed
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if( RegNum == 10000) {
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cout << "\t<*NULL Value*>";
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continue;
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}
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cout << "\t" << "%" << MRI.getUnifiedRegName( RegNum);
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}
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else if( Op.getOperandType() == MachineOperand::MO_PCRelativeDisp ) {
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const Value *const Val = Op.getVRegValue () ;
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if( !Val ) {
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cout << "\t<*NULL Value*>";
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continue;
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}
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if( (Val->getValueType() == Value::BasicBlockVal))
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{ cout << "\t"; printLabel( Op.getVRegValue () ); }
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else { cout << "\t"; printValue( Val ); }
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}
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else
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cout << "\t" << Op; // use dump field
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}
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}
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cout << endl;
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}
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cout << endl;
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}
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void PhyRegAlloc::printLabel(const Value *const Val)
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{
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if( Val->hasName() )
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cout << Val->getName();
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else
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cout << "Label" << Val;
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}
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void PhyRegAlloc::allocateRegisters()
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{
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constructLiveRanges(); // create LR info
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if( DEBUG_RA)
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LRI.printLiveRanges();
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createIGNodeListsAndIGs(); // create IGNode list and IGs
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buildInterferenceGraphs(); // build IGs in all reg classes
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if( DEBUG_RA) {
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// print all LRs in all reg classes
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[ rc ]->printIGNodeList();
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// print IGs in all register classes
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[ rc ]->printIG();
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}
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LRI.coalesceLRs(); // coalesce all live ranges
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if( DEBUG_RA) {
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// print all LRs in all reg classes
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[ rc ]->printIGNodeList();
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// print IGs in all register classes
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[ rc ]->printIG();
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}
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MRI.colorArgs(Meth, LRI); // color method args
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// color call args of call instrns
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MRI.colorCallArgs(CallInstrList, LRI, AddedInstrMap);
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// color all register classes
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for( unsigned int rc=0; rc < NumOfRegClasses ; rc++)
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RegClassList[ rc ]->colorAllRegs();
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updateMachineCode();
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PrintMachineInstructions(Meth);
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printMachineCode(); // only for DEBUGGING
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}
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#if 0
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void PhyRegAlloc::printMachineCode()
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{
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cout << endl << ";************** Method ";
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cout << Meth->getName() << " *****************" << endl;
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Method::const_iterator BBI = Meth->begin(); // random iterator for BBs
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for( ; BBI != Meth->end(); ++BBI) { // traverse BBs in random order
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cout << endl ; printLabel( *BBI); cout << ": ";
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// get the iterator for machine instructions
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MachineCodeForBasicBlock& MIVec = (*BBI)->getMachineInstrVec();
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MachineCodeForBasicBlock::iterator MInstIterator = MIVec.begin();
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// iterate over all the machine instructions in BB
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for( ; MInstIterator != MIVec.end(); ++MInstIterator) {
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MachineInstr *const MInst = *MInstIterator;
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cout << endl << "\t";
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cout << TargetInstrDescriptors[MInst->getOpCode()].opCodeString;
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//for(MachineInstr::val_op_const_iterator OpI(MInst);!OpI.done();++OpI) {
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for(unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
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MachineOperand& Op = MInst->getOperand(OpNum);
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if( Op.getOperandType() == MachineOperand::MO_VirtualRegister ||
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Op.getOperandType() == MachineOperand::MO_CCRegister) {
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const Value *const Val = Op.getVRegValue();
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if( !Val ) {
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cout << "\t<*NULL Value*>";
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continue;
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}
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assert( Val && "Value is NULL");
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const LiveRange *const LR = LRI.getLiveRangeForValue(Val);
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if ( !LR ) {
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if( ! ( (Val->getType())->isLabelType() ||
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(Val->getValueType() == Value::ConstantVal) ) ) {
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cout << "\t" << "<*No LiveRange for: ";
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printValue( Val); cout << "*>";
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}
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//assert( LR && "No LR found for Value");
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continue;
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}
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unsigned RCID = (LR->getRegClass())->getID();
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//cout << "Setting reg for value: "; printValue( Val );
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//cout << endl;
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Op.setRegForValue( MRI.getUnifiedRegNum(RCID, LR->getColor()) );
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int RegNum = MRI.getUnifiedRegNum(RCID, LR->getColor());
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cout << "\t" << "%" << MRI.getUnifiedRegName( RegNum );
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}
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else if( Op.getOperandType() == MachineOperand:: MO_MachineRegister) {
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cout << "\t" << "%"<< MRI.getUnifiedRegName( Op.getMachineRegNum() );
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}
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else if( Op.getOperandType() == MachineOperand::MO_PCRelativeDisp ) {
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const Value *const Val = Op.getVRegValue () ;
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if( !Val ) {
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cout << "\t<*NULL Value*>";
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continue;
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}
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if( (Val->getValueType() == Value::BasicBlockVal))
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{ cout << "\t"; printLabel( Op.getVRegValue () ); }
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else { cout << "\t"; printValue( Val ); }
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}
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else
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cout << "\t" << Op; // use dump field
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}
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}
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cout << endl;
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}
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cout << endl;
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}
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void PhyRegAlloc::printLabel(const Value *const Val)
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{
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if( Val->hasName() )
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cout << Val->getName();
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else
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cout << "Label" << Val;
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}
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#endif
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