mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-27 15:29:51 +00:00
d8149c1bef
parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133736 91177308-0d34-0410-b5e6-96231b3b80d8
25 lines
563 B
LLVM
25 lines
563 B
LLVM
; RUN: llc < %s -march=ptx32 | FileCheck %s
|
|
|
|
; preds
|
|
|
|
define ptx_device i32 @t1_and_preds(i1 %x, i1 %y) {
|
|
; CHECK: and.pred p{{[0-9]+}}, p{{[0-9]+}}, p{{[0-9]+}}
|
|
%c = and i1 %x, %y
|
|
%d = zext i1 %c to i32
|
|
ret i32 %d
|
|
}
|
|
|
|
define ptx_device i32 @t1_or_preds(i1 %x, i1 %y) {
|
|
; CHECK: or.pred p{{[0-9]+}}, p{{[0-9]+}}, p{{[0-9]+}}
|
|
%a = or i1 %x, %y
|
|
%b = zext i1 %a to i32
|
|
ret i32 %b
|
|
}
|
|
|
|
define ptx_device i32 @t1_xor_preds(i1 %x, i1 %y) {
|
|
; CHECK: xor.pred p{{[0-9]+}}, p{{[0-9]+}}, p{{[0-9]+}}
|
|
%a = xor i1 %x, %y
|
|
%b = zext i1 %a to i32
|
|
ret i32 %b
|
|
}
|