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the only real caller (GetFunctionSizeInBytes) uses it. The custom ARM implementation of this is basically reimplementing an assembler poorly for negligible gain. It should be removed IMNSHO, but I'll leave that to ARMish folks to decide. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77877 91177308-0d34-0410-b5e6-96231b3b80d8
232 lines
7.4 KiB
C++
232 lines
7.4 KiB
C++
//===- Thumb1InstrInfo.cpp - Thumb-1 Instruction Information --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Thumb-1 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMInstrInfo.h"
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#include "ARM.h"
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#include "ARMGenInstrInfo.inc"
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#include "ARMMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/ADT/SmallVector.h"
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#include "Thumb1InstrInfo.h"
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using namespace llvm;
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Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI) : RI(*this, STI) {
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}
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unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
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return 0;
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}
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bool
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Thumb1InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
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if (MBB.empty()) return false;
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switch (MBB.back().getOpcode()) {
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case ARM::tBX_RET:
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case ARM::tBX_RET_vararg:
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case ARM::tPOP_RET:
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case ARM::tB:
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case ARM::tBR_JTr:
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return true;
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default:
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break;
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}
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return false;
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}
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bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const {
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (I != MBB.end()) DL = I->getDebugLoc();
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if (DestRC == ARM::GPRRegisterClass) {
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if (SrcRC == ARM::GPRRegisterClass) {
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BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
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return true;
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} else if (SrcRC == ARM::tGPRRegisterClass) {
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BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
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return true;
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}
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} else if (DestRC == ARM::tGPRRegisterClass) {
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if (SrcRC == ARM::GPRRegisterClass) {
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BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
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return true;
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} else if (SrcRC == ARM::tGPRRegisterClass) {
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BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
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return true;
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}
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}
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return false;
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}
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bool Thumb1InstrInfo::
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canFoldMemoryOperand(const MachineInstr *MI,
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const SmallVectorImpl<unsigned> &Ops) const {
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if (Ops.size() != 1) return false;
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unsigned OpNum = Ops[0];
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unsigned Opc = MI->getOpcode();
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switch (Opc) {
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default: break;
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case ARM::tMOVr:
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case ARM::tMOVtgpr2gpr:
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case ARM::tMOVgpr2tgpr:
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case ARM::tMOVgpr2gpr: {
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if (OpNum == 0) { // move -> store
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unsigned SrcReg = MI->getOperand(1).getReg();
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if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
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// tSpill cannot take a high register operand.
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return false;
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} else { // move -> load
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unsigned DstReg = MI->getOperand(0).getReg();
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if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
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// tRestore cannot target a high register operand.
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return false;
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}
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return true;
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}
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}
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return false;
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}
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void Thumb1InstrInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC) const {
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (I != MBB.end()) DL = I->getDebugLoc();
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assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
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if (RC == ARM::tGPRRegisterClass) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI).addImm(0));
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}
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}
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void Thumb1InstrInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC) const {
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (I != MBB.end()) DL = I->getDebugLoc();
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assert(RC == ARM::tGPRRegisterClass && "Unknown regclass!");
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if (RC == ARM::tGPRRegisterClass) {
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AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg)
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.addFrameIndex(FI).addImm(0));
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}
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}
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bool Thumb1InstrInfo::
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spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI) const {
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if (CSI.empty())
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return false;
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, get(ARM::tPUSH));
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for (unsigned i = CSI.size(); i != 0; --i) {
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unsigned Reg = CSI[i-1].getReg();
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// Add the callee-saved register as live-in. It's killed at the spill.
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MBB.addLiveIn(Reg);
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MIB.addReg(Reg, RegState::Kill);
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}
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return true;
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}
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bool Thumb1InstrInfo::
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restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI) const {
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MachineFunction &MF = *MBB.getParent();
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ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
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if (CSI.empty())
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return false;
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bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
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MachineInstr *PopMI = MF.CreateMachineInstr(get(ARM::tPOP),MI->getDebugLoc());
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for (unsigned i = CSI.size(); i != 0; --i) {
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unsigned Reg = CSI[i-1].getReg();
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if (Reg == ARM::LR) {
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// Special epilogue for vararg functions. See emitEpilogue
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if (isVarArg)
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continue;
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Reg = ARM::PC;
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PopMI->setDesc(get(ARM::tPOP_RET));
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MI = MBB.erase(MI);
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}
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PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
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}
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// It's illegal to emit pop instruction without operands.
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if (PopMI->getNumOperands() > 0)
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MBB.insert(MI, PopMI);
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return true;
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}
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MachineInstr *Thumb1InstrInfo::
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foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
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const SmallVectorImpl<unsigned> &Ops, int FI) const {
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if (Ops.size() != 1) return NULL;
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unsigned OpNum = Ops[0];
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unsigned Opc = MI->getOpcode();
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MachineInstr *NewMI = NULL;
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switch (Opc) {
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default: break;
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case ARM::tMOVr:
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case ARM::tMOVtgpr2gpr:
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case ARM::tMOVgpr2tgpr:
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case ARM::tMOVgpr2gpr: {
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if (OpNum == 0) { // move -> store
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unsigned SrcReg = MI->getOperand(1).getReg();
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bool isKill = MI->getOperand(1).isKill();
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if (RI.isPhysicalRegister(SrcReg) && !isARMLowRegister(SrcReg))
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// tSpill cannot take a high register operand.
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break;
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NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tSpill))
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.addReg(SrcReg, getKillRegState(isKill))
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.addFrameIndex(FI).addImm(0));
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} else { // move -> load
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unsigned DstReg = MI->getOperand(0).getReg();
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if (RI.isPhysicalRegister(DstReg) && !isARMLowRegister(DstReg))
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// tRestore cannot target a high register operand.
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break;
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bool isDead = MI->getOperand(0).isDead();
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NewMI = AddDefaultPred(BuildMI(MF, MI->getDebugLoc(), get(ARM::tRestore))
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.addReg(DstReg,
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RegState::Define | getDeadRegState(isDead))
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.addFrameIndex(FI).addImm(0));
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}
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break;
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}
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}
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return NewMI;
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}
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