Saleem Abdulrasool 3455c40f91 CodeGen: enable mov.w/mov.t pairs with minsize for WoA ... Windows on ARM uses COFF/PE which is intrinsically position independent. For the case of 32-bit immediates, use a pair-wise relocation as otherwise we may exceed the range of operators. This fixes a code generation crash when using -Oz when targeting Windows on ARM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@210814 91177308-0d34-0410-b5e6-96231b3b80d8		2014-06-12 20:06:33 +00:00
..
AArch64	[AArch64] Basic Sched Model for Cortex-A57.	2014-06-11 21:06:56 +00:00
ARM	CodeGen: enable mov.w/mov.t pairs with minsize for WoA	2014-06-12 20:06:33 +00:00
CPP	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
Generic	Add a new attribute called 'jumptable' that creates jump-instruction tables for functions marked with this attribute.	2014-06-05 19:29:43 +00:00
Hexagon	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
Inputs
Mips	[mips][mips64r6] bc1[tf] are not available on MIPS32r6/MIPS64r6	2014-06-12 15:00:17 +00:00
MSP430	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
NVPTX	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
PowerPC	[PPC64LE] Recognize shufflevector patterns for little endian	2014-06-10 14:35:01 +00:00
R600	Revert "SelectionDAG: Enable (and (setcc x), (setcc y)) -> (setcc (and x, y)) for vectors"	2014-06-12 16:04:47 +00:00
SPARC	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
SystemZ	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
Thumb	Disable the load/store optimization pass for Thumb-1.	2014-06-12 15:18:33 +00:00
Thumb2	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00
X86	Revert "[FastIsel][X86] Add support for lowering the first 8 floating-point arguments."	2014-06-12 19:21:43 +00:00
XCore	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00