Simon Pilgrim 34630b6ea9 [X86][SSE] Avoid vector byte shuffles with zero by using pshufb to create zeros ... pshufb can shuffle in zero bytes as well as bytes from a source vector - we can use this to avoid having to shuffle 2 vectors and ORing the result when the used inputs from a vector are all zeroable. Differential Revision: http://reviews.llvm.org/D6878 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225551 91177308-0d34-0410-b5e6-96231b3b80d8		2015-01-09 22:03:19 +00:00
..
AArch64	Revert r225165 and r225169	2015-01-07 06:34:34 +00:00
ARM	Fix large stack alignment codegen for ARM and Thumb2 targets	2015-01-08 15:09:14 +00:00
CPP
Generic	CodeGen: do not attempt to invalidate virtual registers for zero-sized phis.	2014-12-19 20:50:07 +00:00
Hexagon	[Hexagon] Adding dealloc_return encoding and absolute address stores.	2015-01-06 16:15:15 +00:00
Inputs	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
Mips	[mips] Add support for accessing $gp as a named register.	2015-01-09 17:21:30 +00:00
MSP430
NVPTX	[NVPTX] Fix bugs related to isSingleValueType	2014-12-17 17:59:04 +00:00
PowerPC	[PowerPC] Fold [sz]ext with fp_to_int lowering where possible	2015-01-09 01:34:30 +00:00
R600	R600/SI: Remove SIISelLowering::legalizeOperands()	2015-01-08 15:08:17 +00:00
SPARC	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
SystemZ	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
Thumb	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
Thumb2	[ARM] Fix a bug in constant island pass that was triggering an assertion.	2015-01-08 20:44:50 +00:00
X86	[X86][SSE] Avoid vector byte shuffles with zero by using pshufb to create zeros	2015-01-09 22:03:19 +00:00
XCore	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00