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https://github.com/c64scene-ar/llvm-6502.git
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3492eefa4b
Since the VSrc_* register classes contain both VGPRs and SGPRs, copies that used be emitted by isel like this: SGPR = COPY VGPR Will now be emitted like this: VSrC = COPY VGPR This patch also adds a pass that tries to identify and fix situations where a VGPR to SGPR copy may occur. Hopefully, these changes will make it impossible for the compiler to generate illegal VGPR to SGPR copies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187831 91177308-0d34-0410-b5e6-96231b3b80d8
85 lines
3.5 KiB
LLVM
85 lines
3.5 KiB
LLVM
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s
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; This test checks that no VGPR to SGPR copies are created by the register
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; allocator.
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; CHECK: @main
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; CHECK: S_BUFFER_LOAD_DWORD [[DST:SGPR[0-9]]], {{[SGPR_[0-9]+}}, 0
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; CHECK: V_MOV_B32_e32 VGPR{{[0-9]}}, [[DST]]
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define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
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main_body:
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%20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
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%21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
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%22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
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%23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 16)
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%24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 32)
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%25 = fptosi float %23 to i32
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%26 = icmp ne i32 %25, 0
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br i1 %26, label %ENDIF, label %ELSE
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ELSE: ; preds = %main_body
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%27 = fsub float -0.000000e+00, %22
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br label %ENDIF
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ENDIF: ; preds = %main_body, %ELSE
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%temp.0 = phi float [ %27, %ELSE ], [ %22, %main_body ]
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%28 = fadd float %temp.0, %24
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %28, float %28, float 0.000000e+00, float 1.000000e+00)
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ret void
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}
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; We just want ot make sure the program doesn't crash
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; CHECK: @loop
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define void @loop(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
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main_body:
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%20 = getelementptr <16 x i8> addrspace(2)* %0, i32 0
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%21 = load <16 x i8> addrspace(2)* %20, !tbaa !0
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%22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 0)
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%23 = call float @llvm.SI.load.const(<16 x i8> %21, i32 4)
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%24 = call float @llvm.SI.load.const(<16 x i8> %21, i32 8)
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%25 = call float @llvm.SI.load.const(<16 x i8> %21, i32 12)
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%26 = fptosi float %25 to i32
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%27 = bitcast i32 %26 to float
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%28 = bitcast float %27 to i32
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br label %LOOP
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LOOP: ; preds = %ENDIF, %main_body
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%temp4.0 = phi float [ %22, %main_body ], [ %temp5.0, %ENDIF ]
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%temp5.0 = phi float [ %23, %main_body ], [ %temp6.0, %ENDIF ]
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%temp6.0 = phi float [ %24, %main_body ], [ %temp4.0, %ENDIF ]
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%temp8.0 = phi float [ 0.000000e+00, %main_body ], [ %37, %ENDIF ]
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%29 = bitcast float %temp8.0 to i32
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%30 = icmp sge i32 %29, %28
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%31 = sext i1 %30 to i32
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%32 = bitcast i32 %31 to float
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%33 = bitcast float %32 to i32
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%34 = icmp ne i32 %33, 0
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br i1 %34, label %IF, label %ENDIF
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IF: ; preds = %LOOP
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %temp4.0, float %temp5.0, float %temp6.0, float 1.000000e+00)
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ret void
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ENDIF: ; preds = %LOOP
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%35 = bitcast float %temp8.0 to i32
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%36 = add i32 %35, 1
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%37 = bitcast i32 %36 to float
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br label %LOOP
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}
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; Function Attrs: nounwind readnone
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declare float @llvm.SI.load.const(<16 x i8>, i32) #1
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; Function Attrs: readonly
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declare float @fabs(float) #2
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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attributes #0 = { "ShaderType"="0" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { readonly }
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!0 = metadata !{metadata !"const", null, i32 1}
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