Tom Stellard 38d5e1c36d R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2 ... Using REG_SEQUENCE for BUILD_VECTOR rather than a series of INSERT_SUBREG instructions should make it easier for the register allocator to coalasce unnecessary copies. v2: - Use an SGPR register class if all the operands of BUILD_VECTOR are SGPRs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188427 91177308-0d34-0410-b5e6-96231b3b80d8		2013-08-14 23:24:32 +00:00
..
Analysis	Fix an oversight in isPotentiallyReachable where we wouldn't do any CFG-walking	2013-08-13 00:03:47 +00:00
AsmParser
Bitcode
CodeGen	DebugInfo: Prefer references over pointers, pass by const reference for a type that will grow in the future	2013-08-14 22:23:05 +00:00
DebugInfo
ExecutionEngine	Optimistically ignore scattered relocations in MachO in RuntimeDyld. This	2013-08-09 00:57:01 +00:00
IR	[Mips][msa] Value types for MSA support.	2013-08-13 22:34:26 +00:00
IRReader
Linker
MC	Support C99 hexadecimal floating-point literals in assembly	2013-08-14 14:23:31 +00:00
Object	Add back missing PPC relocation types.	2013-08-09 09:42:14 +00:00
Option	Options: explicit handling of --	2013-08-13 22:23:05 +00:00
Support	Use the MSVC __cpuid intrinsic instead of inline asm	2013-08-14 18:21:51 +00:00
TableGen	Remove some std stream usage from Support and TableGen	2013-08-06 22:51:21 +00:00
Target	R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2	2013-08-14 23:24:32 +00:00
Transforms	Fix small typo: s/succ/Succ/	2013-08-14 22:11:42 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile