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514d703ff6
for the Cortex-A53 subtarget in the AArch64 backend. This patch lays the ground work to annotate each AArch64 instruction (no NEON yet) with a list of SchedReadWrite types. The patch also provides the Cortex-A53 processor resources, maps those the the default SchedReadWrites, and provides basic latency. NEON support will be added in a subsequent patch with proper forwarding logic. Verification was done by setting the pre-RA scheduler to linearize to better gauge the effect of the MIScheduler. Even without modeling the forward logic, the results show a modest improvement for Cortex-A53. Reviewers: apazos, mcrosier, atrick Patch by Dave Estes <cestes@codeaurora.org>! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203125 91177308-0d34-0410-b5e6-96231b3b80d8
73 lines
2.1 KiB
TableGen
73 lines
2.1 KiB
TableGen
//===- AArch64Schedule.td - AArch64 Scheduling Definitions -*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Generic processor itineraries for legacy compatibility.
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def GenericItineraries : ProcessorItineraries<[], [], []>;
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//===----------------------------------------------------------------------===//
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// Base SchedReadWrite types
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// Basic ALU
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def WriteALU : SchedWrite; // Generic: may contain shift and/or ALU operation
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def WriteALUs : SchedWrite; // Shift only with no ALU operation
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def ReadALU : SchedRead; // Operand not needed for shifting
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def ReadALUs : SchedRead; // Operand needed for shifting
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// Multiply with optional accumulate
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def WriteMAC : SchedWrite;
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def ReadMAC : SchedRead;
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// Compares
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def WriteCMP : SchedWrite;
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def ReadCMP : SchedRead;
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// Division
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def WriteDiv : SchedWrite;
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def ReadDiv : SchedRead;
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// Loads
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def WriteLd : SchedWrite;
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def WritePreLd : SchedWrite;
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def ReadLd : SchedRead;
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def ReadPreLd : SchedRead;
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// Branches
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def WriteBr : SchedWrite;
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def WriteBrL : SchedWrite;
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def ReadBr : SchedRead;
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// Floating Point ALU
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def WriteFPALU : SchedWrite;
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def ReadFPALU : SchedRead;
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// Floating Point MAC, Mul, Div, Sqrt
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// Most processors will simply send all of these down a dedicated pipe, but
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// they're explicitly seperated here for flexibility of modeling later. May
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// consider consolidating them into a single WriteFPXXXX type in the future.
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def WriteFPMAC : SchedWrite;
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def WriteFPMul : SchedWrite;
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def WriteFPDiv : SchedWrite;
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def WriteFPSqrt : SchedWrite;
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def ReadFPMAC : SchedRead;
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def ReadFPMul : SchedRead;
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def ReadFPDiv : SchedRead;
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def ReadFPSqrt : SchedRead;
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// Noop
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def WriteNoop : SchedWrite;
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//===----------------------------------------------------------------------===//
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// Subtarget specific Machine Models.
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include "AArch64ScheduleA53.td"
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