llvm-6502

mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-09 10:05:41 +00:00

History

Roman Divacky 14551f041b Lower FNEG just like FABS to fneg[ds] and fmov[ds], thus avoiding expensive libcall. Also, Qp_neg is not implemented on at least FreeBSD. This is also what gcc is doing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202422 91177308-0d34-0410-b5e6-96231b3b80d8		2014-02-27 19:26:29 +00:00
..
AsmParser	[Sparc] Emit correct encoding for atomic instructions. Also, add support for parsing CAS instructions to test the CAS encoding.	2014-02-07 07:34:49 +00:00
Disassembler	[Sparc] Replace (unsigned)-1 with ~OU as suggested by Reid Kleckner.	2014-01-12 04:34:31 +00:00
InstPrinter	[Sparc] Use SparcMCExpr::VariantKind itself as MachineOperand's target flags.	2014-02-07 02:36:06 +00:00
MCTargetDesc	Re-commit: Demote EmitRawText call in AsmPrinter::EmitInlineAsm() and remove hasRawTextSupport() call	2014-02-13 14:44:26 +00:00
TargetInfo	Prune redundant dependencies in LLVMBuild.txt.	2013-12-11 00:30:57 +00:00
CMakeLists.txt	[Sparc] Use %r_disp32 for pc_rel entries in gcc_except_table and eh_frame.	2014-01-29 04:51:35 +00:00
DelaySlotFiller.cpp	[Sparc] Bundle instruction with delay slow and its filler. Now, we can use -verify-machineinstrs with SPARC backend.	2014-01-11 19:38:03 +00:00
LLVMBuild.txt	[Sparc] Add initial implementation of disassembler for sparc	2014-01-06 08:08:58 +00:00
Makefile	[Sparc] Add initial implementation of disassembler for sparc	2014-01-06 08:08:58 +00:00
README.txt
Sparc.h	[Sparc] Lower and MachineInstr to MC and print assembly using MCInstPrinter.	2013-12-26 01:49:59 +00:00
Sparc.td	Only generate the popc instruction for SPARC CPUs that implement it.	2014-01-26 06:09:59 +00:00
SparcAsmPrinter.cpp	[Sparc] Emit correct relocations for PIC code when integrated assembler is used.	2014-02-07 04:24:35 +00:00
SparcCallingConv.td	The SPARCv9 ABI returns a float in %f0.	2014-01-12 04:13:17 +00:00
SparcCodeEmitter.cpp	[Sparc] Use SparcMCExpr::VariantKind itself as MachineOperand's target flags.	2014-02-07 02:36:06 +00:00
SparcFrameLowering.cpp
SparcFrameLowering.h
SparcInstr64Bit.td	[Sparc] Emit correct encoding for atomic instructions. Also, add support for parsing CAS instructions to test the CAS encoding.	2014-02-07 07:34:49 +00:00
SparcInstrAliases.td	[Sparc] Add support for parsing synthetic instruction 'mov'.	2014-02-07 09:06:52 +00:00
SparcInstrFormats.td	[Sparc] Emit correct encoding for atomic instructions. Also, add support for parsing CAS instructions to test the CAS encoding.	2014-02-07 07:34:49 +00:00
SparcInstrInfo.cpp	[SparcV9] Use correct register class (I64RegClass) to hold the address of _GLOBAL_OFFSET_TABLE_ in sparcv9.	2014-01-29 03:35:08 +00:00
SparcInstrInfo.h
SparcInstrInfo.td	SPARC: Implement TRAP lowering. Matches what GCC emits.	2014-02-23 21:43:52 +00:00
SparcISelDAGToDAG.cpp
SparcISelLowering.cpp	Lower FNEG just like FABS to fneg[ds] and fmov[ds], thus avoiding	2014-02-27 19:26:29 +00:00
SparcISelLowering.h	Implement atomicrmw operations in 32 and 64 bits for SPARCv9.	2014-01-24 06:23:31 +00:00
SparcJITInfo.cpp	[Sparc] Save and restore float registers that may be used for parameter passing.	2014-01-31 01:53:08 +00:00
SparcJITInfo.h
SparcMachineFunctionInfo.cpp
SparcMachineFunctionInfo.h
SparcMCInstLower.cpp	[Sparc] Use SparcMCExpr::VariantKind itself as MachineOperand's target flags.	2014-02-07 02:36:06 +00:00
SparcRegisterInfo.cpp	[Sparc] Set %o7 as the return address register instead of %i7 in MCRegisterInfo. Also, add CFI instructions to initialize the frame correctly.	2014-02-01 18:54:16 +00:00
SparcRegisterInfo.h
SparcRegisterInfo.td	Add a dwarf number to the Y register.	2014-02-24 18:41:31 +00:00
SparcRelocations.h	[SparcV9] Add support for JIT in Sparc64.	2014-01-24 07:10:19 +00:00
SparcSelectionDAGInfo.cpp
SparcSelectionDAGInfo.h
SparcSubtarget.cpp	Clean up the Legal/Expand logic for SPARC popc.	2014-01-26 08:12:34 +00:00
SparcSubtarget.h	Only generate the popc instruction for SPARC CPUs that implement it.	2014-01-26 06:09:59 +00:00
SparcTargetMachine.cpp	Make the llvm mangler depend only on DataLayout.	2014-01-03 19:21:54 +00:00
SparcTargetMachine.h
SparcTargetObjectFile.cpp	move getNameWithPrefix and getSymbol to TargetMachine.	2014-02-19 20:30:41 +00:00
SparcTargetObjectFile.h	Add back r201608, r201622, r201624 and r201625	2014-02-19 17:23:20 +00:00
SparcTargetStreamer.h	Construct the MCStreamer before constructing the MCTargetStreamer.	2014-01-26 06:06:37 +00:00

README.txt

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for
  leaf fns.
* Fill delay slots

* Implement JIT support

* Use %g0 directly to materialize 0. No instruction is required.