mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-07-25 14:30:32 +00:00
352aa503fa
On Nehalem and newer CPUs there is a 2 cycle latency penalty on using a register in a different domain than where it was defined. Some instructions have equvivalents for different domains, like por/orps/orpd. The SSEDomainFix pass tries to minimize the number of domain crossings by changing between equvivalent opcodes where possible. This is a work in progress, in particular the pass doesn't do anything yet. SSE instructions are tagged with their execution domain in TableGen using the last two bits of TSFlags. Note that not all instructions are tagged correctly. Life just isn't that simple. The SSE execution domain issue is very similar to the ARM NEON/VFP pipeline issue handled by NEONMoveFixPass. This pass may become target independent to handle both. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99524 91177308-0d34-0410-b5e6-96231b3b80d8
46 lines
1.3 KiB
CMake
46 lines
1.3 KiB
CMake
set(LLVM_TARGET_DEFINITIONS X86.td)
|
|
|
|
tablegen(X86GenRegisterInfo.h.inc -gen-register-desc-header)
|
|
tablegen(X86GenRegisterNames.inc -gen-register-enums)
|
|
tablegen(X86GenRegisterInfo.inc -gen-register-desc)
|
|
tablegen(X86GenDisassemblerTables.inc -gen-disassembler)
|
|
tablegen(X86GenInstrNames.inc -gen-instr-enums)
|
|
tablegen(X86GenInstrInfo.inc -gen-instr-desc)
|
|
tablegen(X86GenAsmWriter.inc -gen-asm-writer)
|
|
tablegen(X86GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
|
|
tablegen(X86GenAsmMatcher.inc -gen-asm-matcher)
|
|
tablegen(X86GenDAGISel.inc -gen-dag-isel)
|
|
tablegen(X86GenFastISel.inc -gen-fast-isel)
|
|
tablegen(X86GenCallingConv.inc -gen-callingconv)
|
|
tablegen(X86GenSubtarget.inc -gen-subtarget)
|
|
|
|
set(sources
|
|
SSEDomainFix.cpp
|
|
X86AsmBackend.cpp
|
|
X86CodeEmitter.cpp
|
|
X86COFFMachineModuleInfo.cpp
|
|
X86ELFWriterInfo.cpp
|
|
X86FloatingPoint.cpp
|
|
X86FloatingPointRegKill.cpp
|
|
X86ISelDAGToDAG.cpp
|
|
X86ISelLowering.cpp
|
|
X86InstrInfo.cpp
|
|
X86JITInfo.cpp
|
|
X86MCAsmInfo.cpp
|
|
X86MCCodeEmitter.cpp
|
|
X86RegisterInfo.cpp
|
|
X86Subtarget.cpp
|
|
X86TargetMachine.cpp
|
|
X86TargetObjectFile.cpp
|
|
X86FastISel.cpp
|
|
)
|
|
|
|
if( CMAKE_CL_64 )
|
|
enable_language(ASM_MASM)
|
|
set(sources ${sources} X86CompilationCallback_Win64.asm)
|
|
endif()
|
|
|
|
add_llvm_target(X86CodeGen ${sources})
|
|
|
|
target_link_libraries (LLVMX86CodeGen LLVMSelectionDAG)
|