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352aa503fa
On Nehalem and newer CPUs there is a 2 cycle latency penalty on using a register in a different domain than where it was defined. Some instructions have equvivalents for different domains, like por/orps/orpd. The SSEDomainFix pass tries to minimize the number of domain crossings by changing between equvivalent opcodes where possible. This is a work in progress, in particular the pass doesn't do anything yet. SSE instructions are tagged with their execution domain in TableGen using the last two bits of TSFlags. Note that not all instructions are tagged correctly. Life just isn't that simple. The SSE execution domain issue is very similar to the ARM NEON/VFP pipeline issue handled by NEONMoveFixPass. This pass may become target independent to handle both. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99524 91177308-0d34-0410-b5e6-96231b3b80d8
225 lines
10 KiB
TableGen
225 lines
10 KiB
TableGen
//===- X86.td - Target definition file for the Intel X86 ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This is a target description file for the Intel i386 architecture, refered to
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// here as the "X86" architecture.
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//
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//===----------------------------------------------------------------------===//
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// Get the target-independent interfaces which we are implementing...
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//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// X86 Subtarget features.
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//===----------------------------------------------------------------------===//
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def FeatureCMOV : SubtargetFeature<"cmov","HasCMov", "true",
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"Enable conditional move instructions">;
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def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX",
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"Enable MMX instructions">;
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def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
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"Enable SSE instructions",
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// SSE codegen depends on cmovs, and all
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// SSE1+ processors support them.
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[FeatureMMX, FeatureCMOV]>;
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def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
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"Enable SSE2 instructions",
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[FeatureSSE1]>;
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def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
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"Enable SSE3 instructions",
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[FeatureSSE2]>;
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def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
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"Enable SSSE3 instructions",
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[FeatureSSE3]>;
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def FeatureSSE41 : SubtargetFeature<"sse41", "X86SSELevel", "SSE41",
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"Enable SSE 4.1 instructions",
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[FeatureSSSE3]>;
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def FeatureSSE42 : SubtargetFeature<"sse42", "X86SSELevel", "SSE42",
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"Enable SSE 4.2 instructions",
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[FeatureSSE41]>;
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def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
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"Enable 3DNow! instructions">;
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def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
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"Enable 3DNow! Athlon instructions",
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[Feature3DNow]>;
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// All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
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// feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
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// without disabling 64-bit mode.
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def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
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"Support 64-bit instructions",
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[FeatureCMOV]>;
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def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
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"Bit testing of memory is slow">;
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def FeatureSSE4A : SubtargetFeature<"sse4a", "HasSSE4A", "true",
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"Support SSE 4a instructions">;
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def FeatureAVX : SubtargetFeature<"avx", "HasAVX", "true",
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"Enable AVX instructions">;
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def FeatureFMA3 : SubtargetFeature<"fma3", "HasFMA3", "true",
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"Enable three-operand fused multiple-add">;
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def FeatureFMA4 : SubtargetFeature<"fma4", "HasFMA4", "true",
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"Enable four-operand fused multiple-add">;
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def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
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"HasVectorUAMem", "true",
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"Allow unaligned memory operands on vector/SIMD instructions">;
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//===----------------------------------------------------------------------===//
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// X86 processors supported.
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//===----------------------------------------------------------------------===//
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class Proc<string Name, list<SubtargetFeature> Features>
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: Processor<Name, NoItineraries, Features>;
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def : Proc<"generic", []>;
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def : Proc<"i386", []>;
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def : Proc<"i486", []>;
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def : Proc<"i586", []>;
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def : Proc<"pentium", []>;
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def : Proc<"pentium-mmx", [FeatureMMX]>;
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def : Proc<"i686", []>;
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def : Proc<"pentiumpro", [FeatureCMOV]>;
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def : Proc<"pentium2", [FeatureMMX, FeatureCMOV]>;
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def : Proc<"pentium3", [FeatureSSE1]>;
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def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>;
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def : Proc<"pentium4", [FeatureSSE2]>;
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def : Proc<"x86-64", [FeatureSSE2, Feature64Bit, FeatureSlowBTMem]>;
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def : Proc<"yonah", [FeatureSSE3, FeatureSlowBTMem]>;
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def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
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def : Proc<"nocona", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>;
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def : Proc<"core2", [FeatureSSSE3, Feature64Bit, FeatureSlowBTMem]>;
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def : Proc<"penryn", [FeatureSSE41, Feature64Bit, FeatureSlowBTMem]>;
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def : Proc<"atom", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>;
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def : Proc<"corei7", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem]>;
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def : Proc<"nehalem", [FeatureSSE42, Feature64Bit, FeatureSlowBTMem]>;
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// Sandy Bridge does not have FMA
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def : Proc<"sandybridge", [FeatureSSE42, FeatureAVX, Feature64Bit]>;
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def : Proc<"k6", [FeatureMMX]>;
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def : Proc<"k6-2", [FeatureMMX, Feature3DNow]>;
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def : Proc<"k6-3", [FeatureMMX, Feature3DNow]>;
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def : Proc<"athlon", [FeatureMMX, Feature3DNowA, FeatureSlowBTMem]>;
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def : Proc<"athlon-tbird", [FeatureMMX, Feature3DNowA, FeatureSlowBTMem]>;
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def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
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def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
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def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
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def : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit,
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FeatureSlowBTMem]>;
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def : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit,
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FeatureSlowBTMem]>;
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def : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit,
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FeatureSlowBTMem]>;
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def : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit,
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FeatureSlowBTMem]>;
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def : Proc<"k8-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit,
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FeatureSlowBTMem]>;
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def : Proc<"opteron-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit,
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FeatureSlowBTMem]>;
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def : Proc<"athlon64-sse3", [FeatureSSE3, Feature3DNowA, Feature64Bit,
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FeatureSlowBTMem]>;
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def : Proc<"amdfam10", [FeatureSSE3, FeatureSSE4A,
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Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
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def : Proc<"barcelona", [FeatureSSE3, FeatureSSE4A,
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Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
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def : Proc<"istanbul", [Feature3DNowA, Feature64Bit, FeatureSSE4A,
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Feature3DNowA]>;
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def : Proc<"shanghai", [Feature3DNowA, Feature64Bit, FeatureSSE4A,
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Feature3DNowA]>;
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def : Proc<"winchip-c6", [FeatureMMX]>;
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def : Proc<"winchip2", [FeatureMMX, Feature3DNow]>;
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def : Proc<"c3", [FeatureMMX, Feature3DNow]>;
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def : Proc<"c3-2", [FeatureSSE1]>;
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "X86RegisterInfo.td"
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//===----------------------------------------------------------------------===//
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// Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "X86InstrInfo.td"
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def X86InstrInfo : InstrInfo {
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// Define how we want to layout our TargetSpecific information field... This
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// should be kept up-to-date with the fields in the X86InstrInfo.h file.
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let TSFlagsFields = ["FormBits",
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"hasOpSizePrefix",
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"hasAdSizePrefix",
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"Prefix",
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"hasREX_WPrefix",
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"ImmTypeBits",
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"FPFormBits",
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"hasLockPrefix",
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"SegOvrBits",
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"DomainBits",
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"Opcode"];
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let TSFlagsShifts = [0,
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6,
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7,
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8,
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12,
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13,
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16,
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19,
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20,
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22,
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24];
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}
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//===----------------------------------------------------------------------===//
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// Calling Conventions
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//===----------------------------------------------------------------------===//
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include "X86CallingConv.td"
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//===----------------------------------------------------------------------===//
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// Assembly Printers
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//===----------------------------------------------------------------------===//
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// Currently the X86 assembly parser only supports ATT syntax.
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def ATTAsmParser : AsmParser {
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string AsmParserClassName = "ATTAsmParser";
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string AsmParserInstCleanup = "InstructionCleanup";
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int Variant = 0;
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// Discard comments in assembly strings.
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string CommentDelimiter = "#";
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// Recognize hard coded registers.
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string RegisterPrefix = "%";
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}
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// The X86 target supports two different syntaxes for emitting machine code.
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// This is controlled by the -x86-asm-syntax={att|intel}
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def ATTAsmWriter : AsmWriter {
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string AsmWriterClassName = "ATTInstPrinter";
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int Variant = 0;
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}
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def IntelAsmWriter : AsmWriter {
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string AsmWriterClassName = "IntelInstPrinter";
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int Variant = 1;
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}
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def X86 : Target {
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// Information about the instructions...
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let InstructionSet = X86InstrInfo;
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let AssemblyParsers = [ATTAsmParser];
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let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
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}
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