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https://github.com/c64scene-ar/llvm-6502.git
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d71295a684
implementation of a Target{RegInfo, InstrInfo, Machine, etc} now has a separate
header and a separate implementation file.
This means that instead of a massive SparcInternals.h that forces a
recompilation of the whole target whenever a minor detail is changed, you should
only recompile a few files.
Note that SparcInternals.h is still around; its contents should be minimized.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10500 91177308-0d34-0410-b5e6-96231b3b80d8
202 lines
9.1 KiB
C++
202 lines
9.1 KiB
C++
//===-- SparcInstrInfo.h - Define TargetInstrInfo for Sparc -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This class contains information about individual instructions.
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// Most information is stored in the SparcMachineInstrDesc array above.
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// Other information is computed on demand, and most such functions
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// default to member functions in base class TargetInstrInfo.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SPARC_INSTRINFO_H
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#define SPARC_INSTRINFO_H
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "SparcInternals.h"
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namespace llvm {
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struct SparcInstrInfo : public TargetInstrInfo {
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SparcInstrInfo();
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// All immediate constants are in position 1 except the
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// store instructions and SETxx.
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//
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virtual int getImmedConstantPos(MachineOpCode opCode) const {
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bool ignore;
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if (this->maxImmedConstant(opCode, ignore) != 0) {
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// 1st store opcode
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assert(! this->isStore((MachineOpCode) V9::STBr - 1));
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// last store opcode
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assert(! this->isStore((MachineOpCode) V9::STXFSRi + 1));
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if (opCode == V9::SETSW || opCode == V9::SETUW ||
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opCode == V9::SETX || opCode == V9::SETHI)
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return 0;
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if (opCode >= V9::STBr && opCode <= V9::STXFSRi)
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return 2;
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return 1;
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}
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else
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return -1;
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}
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/// createNOPinstr - returns the target's implementation of NOP, which is
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/// usually a pseudo-instruction, implemented by a degenerate version of
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/// another instruction, e.g. X86: xchg ax, ax; SparcV9: sethi 0, g0
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///
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MachineInstr* createNOPinstr() const {
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return BuildMI(V9::SETHI, 2).addZImm(0).addReg(SparcIntRegClass::g0);
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}
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/// isNOPinstr - not having a special NOP opcode, we need to know if a given
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/// instruction is interpreted as an `official' NOP instr, i.e., there may be
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/// more than one way to `do nothing' but only one canonical way to slack off.
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///
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bool isNOPinstr(const MachineInstr &MI) const {
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// Make sure the instruction is EXACTLY `sethi g0, 0'
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if (MI.getOpcode() == V9::SETHI && MI.getNumOperands() == 2) {
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const MachineOperand &op0 = MI.getOperand(0), &op1 = MI.getOperand(1);
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if (op0.isImmediate() && op0.getImmedValue() == 0 &&
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op1.isMachineRegister() &&
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op1.getMachineRegNum() == SparcIntRegClass::g0)
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{
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return true;
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}
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}
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return false;
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}
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virtual bool hasResultInterlock(MachineOpCode opCode) const
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{
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// All UltraSPARC instructions have interlocks (note that delay slots
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// are not considered here).
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// However, instructions that use the result of an FCMP produce a
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// 9-cycle stall if they are issued less than 3 cycles after the FCMP.
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// Force the compiler to insert a software interlock (i.e., gap of
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// 2 other groups, including NOPs if necessary).
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return (opCode == V9::FCMPS || opCode == V9::FCMPD || opCode == V9::FCMPQ);
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}
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//-------------------------------------------------------------------------
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// Queries about representation of LLVM quantities (e.g., constants)
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//-------------------------------------------------------------------------
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virtual bool ConstantMayNotFitInImmedField(const Constant* CV,
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const Instruction* I) const;
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//-------------------------------------------------------------------------
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// Code generation support for creating individual machine instructions
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//-------------------------------------------------------------------------
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// Get certain common op codes for the current target. This and all the
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// Create* methods below should be moved to a machine code generation class
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//
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virtual MachineOpCode getNOPOpCode() const { return V9::NOP; }
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// Get the value of an integral constant in the form that must
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// be put into the machine register. The specified constant is interpreted
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// as (i.e., converted if necessary to) the specified destination type. The
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// result is always returned as an uint64_t, since the representation of
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// int64_t and uint64_t are identical. The argument can be any known const.
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//
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// isValidConstant is set to true if a valid constant was found.
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//
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virtual uint64_t ConvertConstantToIntType(const TargetMachine &target,
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const Value *V,
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const Type *destType,
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bool &isValidConstant) const;
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// Create an instruction sequence to put the constant `val' into
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// the virtual register `dest'. `val' may be a Constant or a
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// GlobalValue, viz., the constant address of a global variable or function.
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// The generated instructions are returned in `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateCodeToLoadConst(const TargetMachine& target,
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Function* F,
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const;
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// Create an instruction sequence to copy an integer value `val'
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// to a floating point value `dest' by copying to memory and back.
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// val must be an integral type. dest must be a Float or Double.
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// The generated instructions are returned in `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
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Function* F,
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const;
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// Similarly, create an instruction sequence to copy an FP value
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// `val' to an integer value `dest' by copying to memory and back.
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// The generated instructions are returned in `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
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Function* F,
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Value* val,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const;
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// Create instruction(s) to copy src to dest, for arbitrary types
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// The generated instructions are returned in `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateCopyInstructionsByType(const TargetMachine& target,
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Function* F,
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Value* src,
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Instruction* dest,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const;
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// Create instruction sequence to produce a sign-extended register value
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// from an arbitrary sized value (sized in bits, not bytes).
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// The generated instructions are appended to `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateSignExtensionInstructions(const TargetMachine& target,
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Function* F,
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Value* srcVal,
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Value* destVal,
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unsigned int numLowBits,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const;
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// Create instruction sequence to produce a zero-extended register value
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// from an arbitrary sized value (sized in bits, not bytes).
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// The generated instructions are appended to `mvec'.
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// Any temp. registers (TmpInstruction) created are recorded in mcfi.
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// Any stack space required is allocated via mcff.
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//
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virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
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Function* F,
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Value* srcVal,
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Value* destVal,
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unsigned int numLowBits,
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std::vector<MachineInstr*>& mvec,
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MachineCodeForInstruction& mcfi) const;
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};
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} // End llvm namespace
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#endif
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