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b8e9ac834a
Minor code duplication cleanup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76124 91177308-0d34-0410-b5e6-96231b3b80d8
111 lines
3.4 KiB
C++
111 lines
3.4 KiB
C++
//===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Thumb-2 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "ARMInstrInfo.h"
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#include "ARM.h"
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#include "ARMGenInstrInfo.inc"
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#include "ARMMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/ADT/SmallVector.h"
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#include "Thumb2InstrInfo.h"
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using namespace llvm;
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Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
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: ARMBaseInstrInfo(STI), RI(*this, STI) {
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}
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unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
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// FIXME
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return 0;
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}
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unsigned Thumb2InstrInfo::getOpcode(ARMII::Op Op) const {
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switch (Op) {
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case ARMII::ADDri: return ARM::t2ADDri;
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case ARMII::ADDrs: return ARM::t2ADDrs;
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case ARMII::ADDrr: return ARM::t2ADDrr;
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case ARMII::B: return ARM::t2B;
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case ARMII::Bcc: return ARM::t2Bcc;
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case ARMII::BR_JTr: return ARM::t2BR_JTr;
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case ARMII::BR_JTm: return ARM::t2BR_JTm;
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case ARMII::BR_JTadd: return ARM::t2BR_JTadd;
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case ARMII::BX_RET: return ARM::tBX_RET;
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case ARMII::FCPYS: return ARM::FCPYS;
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case ARMII::FCPYD: return ARM::FCPYD;
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case ARMII::FLDD: return ARM::FLDD;
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case ARMII::FLDS: return ARM::FLDS;
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case ARMII::FSTD: return ARM::FSTD;
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case ARMII::FSTS: return ARM::FSTS;
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case ARMII::LDR: return ARM::LDR; // FIXME
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case ARMII::MOVr: return ARM::t2MOVr;
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case ARMII::STR: return ARM::STR; // FIXME
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case ARMII::SUBri: return ARM::t2SUBri;
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case ARMII::SUBrs: return ARM::t2SUBrs;
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case ARMII::SUBrr: return ARM::t2SUBrr;
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case ARMII::VMOVD: return ARM::VMOVD;
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case ARMII::VMOVQ: return ARM::VMOVQ;
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default:
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break;
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}
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return 0;
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}
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bool
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Thumb2InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
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if (MBB.empty()) return false;
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// FIXME
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switch (MBB.back().getOpcode()) {
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case ARM::t2LDM_RET:
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case ARM::t2B: // Uncond branch.
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case ARM::t2BR_JTr: // Jumptable branch.
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case ARM::t2BR_JTm: // Jumptable branch through mem.
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case ARM::t2BR_JTadd: // Jumptable branch add to pc.
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return true;
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case ARM::tBX_RET:
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case ARM::tBX_RET_vararg:
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case ARM::tPOP_RET:
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case ARM::tB:
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case ARM::tBR_JTr:
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return true;
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default:
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break;
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}
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return false;
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}
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bool
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Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const {
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (I != MBB.end()) DL = I->getDebugLoc();
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if ((DestRC == ARM::GPRRegisterClass &&
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SrcRC == ARM::tGPRRegisterClass) ||
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(DestRC == ARM::tGPRRegisterClass &&
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SrcRC == ARM::GPRRegisterClass)) {
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AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(getOpcode(ARMII::MOVr)),
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DestReg).addReg(SrcReg)));
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return true;
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}
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return ARMBaseInstrInfo::copyRegToReg(MBB, I, DestReg, SrcReg, DestRC, SrcRC);
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}
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