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ed143b7c0c
The operand that must match one of the others does matter, and implement selecting for it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211523 91177308-0d34-0410-b5e6-96231b3b80d8
49 lines
2.3 KiB
LLVM
49 lines
2.3 KiB
LLVM
; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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declare { float, i1 } @llvm.AMDGPU.div.scale.f32(float, float, i1) nounwind readnone
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declare { double, i1 } @llvm.AMDGPU.div.scale.f64(double, double, i1) nounwind readnone
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; SI-LABEL @test_div_scale_f32_1:
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; SI: V_DIV_SCALE_F32
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define void @test_div_scale_f32_1(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr) nounwind {
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%a = load float addrspace(1)* %aptr, align 4
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%b = load float addrspace(1)* %bptr, align 4
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%result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 false) nounwind readnone
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%result0 = extractvalue { float, i1 } %result, 0
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store float %result0, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL @test_div_scale_f32_2:
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; SI: V_DIV_SCALE_F32
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define void @test_div_scale_f32_2(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr) nounwind {
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%a = load float addrspace(1)* %aptr, align 4
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%b = load float addrspace(1)* %bptr, align 4
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%result = call { float, i1 } @llvm.AMDGPU.div.scale.f32(float %a, float %b, i1 true) nounwind readnone
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%result0 = extractvalue { float, i1 } %result, 0
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store float %result0, float addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL @test_div_scale_f64_1:
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; SI: V_DIV_SCALE_F64
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define void @test_div_scale_f64_1(double addrspace(1)* %out, double addrspace(1)* %aptr, double addrspace(1)* %bptr, double addrspace(1)* %cptr) nounwind {
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%a = load double addrspace(1)* %aptr, align 8
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%b = load double addrspace(1)* %bptr, align 8
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%result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 false) nounwind readnone
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%result0 = extractvalue { double, i1 } %result, 0
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store double %result0, double addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL @test_div_scale_f64_1:
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; SI: V_DIV_SCALE_F64
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define void @test_div_scale_f64_2(double addrspace(1)* %out, double addrspace(1)* %aptr, double addrspace(1)* %bptr, double addrspace(1)* %cptr) nounwind {
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%a = load double addrspace(1)* %aptr, align 8
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%b = load double addrspace(1)* %bptr, align 8
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%result = call { double, i1 } @llvm.AMDGPU.div.scale.f64(double %a, double %b, i1 true) nounwind readnone
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%result0 = extractvalue { double, i1 } %result, 0
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store double %result0, double addrspace(1)* %out, align 8
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ret void
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}
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