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https://github.com/c64scene-ar/llvm-6502.git
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359b65f782
allocaton on the X86 to add information to the machine code denoting that our floating point stackifier cannot handle virtual point register that are alive across basic blocks. This pass adds an implicit def of all virtual floating point register at the end of each basic block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10446 91177308-0d34-0410-b5e6-96231b3b80d8
657 lines
23 KiB
C++
657 lines
23 KiB
C++
//===-- FloatingPoint.cpp - Floating point Reg -> Stack converter ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the pass which converts floating point instructions from
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// virtual registers into register stack instructions.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "fp"
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/LiveVariables.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "Support/Debug.h"
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#include "Support/Statistic.h"
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#include <algorithm>
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#include <iostream>
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namespace llvm {
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namespace {
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Statistic<> NumFXCH("x86-codegen", "Number of fxch instructions inserted");
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Statistic<> NumFP ("x86-codegen", "Number of floating point instructions");
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struct FPS : public MachineFunctionPass {
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual const char *getPassName() const { return "X86 FP Stackifier"; }
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<LiveVariables>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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private:
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LiveVariables *LV; // Live variable info for current function...
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MachineBasicBlock *MBB; // Current basic block
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unsigned Stack[8]; // FP<n> Registers in each stack slot...
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unsigned RegMap[8]; // Track which stack slot contains each register
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unsigned StackTop; // The current top of the FP stack.
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void dumpStack() const {
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std::cerr << "Stack contents:";
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for (unsigned i = 0; i != StackTop; ++i) {
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std::cerr << " FP" << Stack[i];
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assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
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}
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std::cerr << "\n";
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}
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private:
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// getSlot - Return the stack slot number a particular register number is
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// in...
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unsigned getSlot(unsigned RegNo) const {
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assert(RegNo < 8 && "Regno out of range!");
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return RegMap[RegNo];
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}
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// getStackEntry - Return the X86::FP<n> register in register ST(i)
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unsigned getStackEntry(unsigned STi) const {
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assert(STi < StackTop && "Access past stack top!");
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return Stack[StackTop-1-STi];
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}
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// getSTReg - Return the X86::ST(i) register which contains the specified
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// FP<RegNo> register
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unsigned getSTReg(unsigned RegNo) const {
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return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0;
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}
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// pushReg - Push the specifiex FP<n> register onto the stack
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void pushReg(unsigned Reg) {
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assert(Reg < 8 && "Register number out of range!");
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assert(StackTop < 8 && "Stack overflow!");
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Stack[StackTop] = Reg;
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RegMap[Reg] = StackTop++;
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}
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bool isAtTop(unsigned RegNo) const { return getSlot(RegNo) == StackTop-1; }
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void moveToTop(unsigned RegNo, MachineBasicBlock::iterator &I) {
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if (!isAtTop(RegNo)) {
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unsigned Slot = getSlot(RegNo);
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unsigned STReg = getSTReg(RegNo);
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unsigned RegOnTop = getStackEntry(0);
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// Swap the slots the regs are in
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std::swap(RegMap[RegNo], RegMap[RegOnTop]);
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// Swap stack slot contents
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assert(RegMap[RegOnTop] < StackTop);
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std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
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// Emit an fxch to update the runtime processors version of the state
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MachineInstr *MI = BuildMI(X86::FXCH, 1).addReg(STReg);
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I = 1+MBB->insert(I, MI);
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NumFXCH++;
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}
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}
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void duplicateToTop(unsigned RegNo, unsigned AsReg,
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MachineBasicBlock::iterator &I) {
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unsigned STReg = getSTReg(RegNo);
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pushReg(AsReg); // New register on top of stack
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MachineInstr *MI = BuildMI(X86::FLDrr, 1).addReg(STReg);
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I = 1+MBB->insert(I, MI);
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}
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// popStackAfter - Pop the current value off of the top of the FP stack
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// after the specified instruction.
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void popStackAfter(MachineBasicBlock::iterator &I);
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bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
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void handleZeroArgFP(MachineBasicBlock::iterator &I);
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void handleOneArgFP(MachineBasicBlock::iterator &I);
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void handleTwoArgFP(MachineBasicBlock::iterator &I);
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void handleSpecialFP(MachineBasicBlock::iterator &I);
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};
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}
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FunctionPass *createX86FloatingPointStackifierPass() { return new FPS(); }
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/// runOnMachineFunction - Loop over all of the basic blocks, transforming FP
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/// register references into FP stack references.
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///
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bool FPS::runOnMachineFunction(MachineFunction &MF) {
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LV = &getAnalysis<LiveVariables>();
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StackTop = 0;
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bool Changed = false;
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for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
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Changed |= processBasicBlock(MF, *I);
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return Changed;
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}
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/// processBasicBlock - Loop over all of the instructions in the basic block,
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/// transforming FP instructions into their stack form.
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///
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bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
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const TargetInstrInfo &TII = MF.getTarget().getInstrInfo();
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bool Changed = false;
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MBB = &BB;
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for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
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MachineInstr *MI = *I;
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MachineInstr *PrevMI = I == BB.begin() ? 0 : *(I-1);
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unsigned Flags = TII.get(MI->getOpcode()).TSFlags;
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if ((Flags & X86II::FPTypeMask) == 0) continue; // Ignore non-fp insts!
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++NumFP; // Keep track of # of pseudo instrs
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DEBUG(std::cerr << "\nFPInst:\t";
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MI->print(std::cerr, MF.getTarget()));
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// Get dead variables list now because the MI pointer may be deleted as part
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// of processing!
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LiveVariables::killed_iterator IB = LV->dead_begin(MI);
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LiveVariables::killed_iterator IE = LV->dead_end(MI);
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DEBUG(const MRegisterInfo *MRI = MF.getTarget().getRegisterInfo();
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LiveVariables::killed_iterator I = LV->killed_begin(MI);
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LiveVariables::killed_iterator E = LV->killed_end(MI);
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if (I != E) {
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std::cerr << "Killed Operands:";
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for (; I != E; ++I)
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std::cerr << " %" << MRI->getName(I->second);
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std::cerr << "\n";
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});
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switch (Flags & X86II::FPTypeMask) {
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case X86II::ZeroArgFP: handleZeroArgFP(I); break;
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case X86II::OneArgFP: handleOneArgFP(I); break;
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case X86II::OneArgFPRW: // ST(0) = fsqrt(ST(0))
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assert(0 && "FP instr type not handled yet!");
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case X86II::TwoArgFP: handleTwoArgFP(I); break;
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case X86II::SpecialFP: handleSpecialFP(I); break;
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default: assert(0 && "Unknown FP Type!");
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}
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// Check to see if any of the values defined by this instruction are dead
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// after definition. If so, pop them.
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for (; IB != IE; ++IB) {
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unsigned Reg = IB->second;
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if (Reg >= X86::FP0 && Reg <= X86::FP6) {
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DEBUG(std::cerr << "Register FP#" << Reg-X86::FP0 << " is dead!\n");
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++I; // Insert fxch AFTER the instruction
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moveToTop(Reg-X86::FP0, I); // Insert fxch if necessary
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--I; // Move to fxch or old instruction
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popStackAfter(I); // Pop the top of the stack, killing value
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}
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}
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// Print out all of the instructions expanded to if -debug
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DEBUG(if (*I == PrevMI) {
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std::cerr<< "Just deleted pseudo instruction\n";
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} else {
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MachineBasicBlock::iterator Start = I;
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// Rewind to first instruction newly inserted.
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while (Start != BB.begin() && *(Start-1) != PrevMI) --Start;
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std::cerr << "Inserted instructions:\n\t";
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(*Start)->print(std::cerr, MF.getTarget());
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while (++Start != I+1);
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}
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dumpStack();
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);
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Changed = true;
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}
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assert(StackTop == 0 && "Stack not empty at end of basic block?");
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return Changed;
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}
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//===----------------------------------------------------------------------===//
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// Efficient Lookup Table Support
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//===----------------------------------------------------------------------===//
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struct TableEntry {
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unsigned from;
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unsigned to;
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bool operator<(const TableEntry &TE) const { return from < TE.from; }
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bool operator<(unsigned V) const { return from < V; }
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};
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static bool TableIsSorted(const TableEntry *Table, unsigned NumEntries) {
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for (unsigned i = 0; i != NumEntries-1; ++i)
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if (!(Table[i] < Table[i+1])) return false;
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return true;
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}
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static int Lookup(const TableEntry *Table, unsigned N, unsigned Opcode) {
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const TableEntry *I = std::lower_bound(Table, Table+N, Opcode);
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if (I != Table+N && I->from == Opcode)
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return I->to;
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return -1;
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}
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#define ARRAY_SIZE(TABLE) \
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(sizeof(TABLE)/sizeof(TABLE[0]))
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#ifdef NDEBUG
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#define ASSERT_SORTED(TABLE)
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#else
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#define ASSERT_SORTED(TABLE) \
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{ static bool TABLE##Checked = false; \
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if (!TABLE##Checked) \
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assert(TableIsSorted(TABLE, ARRAY_SIZE(TABLE)) && \
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"All lookup tables must be sorted for efficient access!"); \
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}
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#endif
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//===----------------------------------------------------------------------===//
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// Helper Methods
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//===----------------------------------------------------------------------===//
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// PopTable - Sorted map of instructions to their popping version. The first
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// element is an instruction, the second is the version which pops.
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//
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static const TableEntry PopTable[] = {
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{ X86::FADDrST0 , X86::FADDPrST0 },
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{ X86::FDIVRrST0, X86::FDIVRPrST0 },
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{ X86::FDIVrST0 , X86::FDIVPrST0 },
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{ X86::FISTr16 , X86::FISTPr16 },
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{ X86::FISTr32 , X86::FISTPr32 },
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{ X86::FMULrST0 , X86::FMULPrST0 },
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{ X86::FSTr32 , X86::FSTPr32 },
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{ X86::FSTr64 , X86::FSTPr64 },
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{ X86::FSTrr , X86::FSTPrr },
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{ X86::FSUBRrST0, X86::FSUBRPrST0 },
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{ X86::FSUBrST0 , X86::FSUBPrST0 },
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{ X86::FUCOMPr , X86::FUCOMPPr },
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{ X86::FUCOMr , X86::FUCOMPr },
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};
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/// popStackAfter - Pop the current value off of the top of the FP stack after
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/// the specified instruction. This attempts to be sneaky and combine the pop
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/// into the instruction itself if possible. The iterator is left pointing to
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/// the last instruction, be it a new pop instruction inserted, or the old
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/// instruction if it was modified in place.
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///
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void FPS::popStackAfter(MachineBasicBlock::iterator &I) {
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ASSERT_SORTED(PopTable);
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assert(StackTop > 0 && "Cannot pop empty stack!");
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RegMap[Stack[--StackTop]] = ~0; // Update state
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// Check to see if there is a popping version of this instruction...
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int Opcode = Lookup(PopTable, ARRAY_SIZE(PopTable), (*I)->getOpcode());
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if (Opcode != -1) {
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(*I)->setOpcode(Opcode);
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if (Opcode == X86::FUCOMPPr)
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(*I)->RemoveOperand(0);
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} else { // Insert an explicit pop
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MachineInstr *MI = BuildMI(X86::FSTPrr, 1).addReg(X86::ST0);
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I = MBB->insert(I+1, MI);
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}
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}
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static unsigned getFPReg(const MachineOperand &MO) {
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assert(MO.isPhysicalRegister() && "Expected an FP register!");
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unsigned Reg = MO.getReg();
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assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!");
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return Reg - X86::FP0;
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}
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//===----------------------------------------------------------------------===//
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// Instruction transformation implementation
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//===----------------------------------------------------------------------===//
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/// handleZeroArgFP - ST(0) = fld0 ST(0) = flds <mem>
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//
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void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
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MachineInstr *MI = *I;
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unsigned DestReg = getFPReg(MI->getOperand(0));
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MI->RemoveOperand(0); // Remove the explicit ST(0) operand
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// Result gets pushed on the stack...
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pushReg(DestReg);
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}
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/// handleOneArgFP - fst ST(0), <mem>
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//
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void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
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MachineInstr *MI = *I;
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assert(MI->getNumOperands() == 5 && "Can only handle fst* instructions!");
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unsigned Reg = getFPReg(MI->getOperand(4));
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bool KillsSrc = false;
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for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
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E = LV->killed_end(MI); KI != E; ++KI)
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KillsSrc |= KI->second == X86::FP0+Reg;
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// FSTPr80 and FISTPr64 are strange because there are no non-popping versions.
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// If we have one _and_ we don't want to pop the operand, duplicate the value
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// on the stack instead of moving it. This ensure that popping the value is
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// always ok.
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//
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if ((MI->getOpcode() == X86::FSTPr80 ||
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MI->getOpcode() == X86::FISTPr64) && !KillsSrc) {
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duplicateToTop(Reg, 7 /*temp register*/, I);
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} else {
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moveToTop(Reg, I); // Move to the top of the stack...
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}
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MI->RemoveOperand(4); // Remove explicit ST(0) operand
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if (MI->getOpcode() == X86::FSTPr80 || MI->getOpcode() == X86::FISTPr64) {
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assert(StackTop > 0 && "Stack empty??");
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--StackTop;
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} else if (KillsSrc) { // Last use of operand?
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popStackAfter(I);
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}
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}
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//===----------------------------------------------------------------------===//
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// Define tables of various ways to map pseudo instructions
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//
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// ForwardST0Table - Map: A = B op C into: ST(0) = ST(0) op ST(i)
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static const TableEntry ForwardST0Table[] = {
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{ X86::FpADD, X86::FADDST0r },
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{ X86::FpDIV, X86::FDIVST0r },
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{ X86::FpMUL, X86::FMULST0r },
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{ X86::FpSUB, X86::FSUBST0r },
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{ X86::FpUCOM, X86::FUCOMr },
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};
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// ReverseST0Table - Map: A = B op C into: ST(0) = ST(i) op ST(0)
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static const TableEntry ReverseST0Table[] = {
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{ X86::FpADD, X86::FADDST0r }, // commutative
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{ X86::FpDIV, X86::FDIVRST0r },
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{ X86::FpMUL, X86::FMULST0r }, // commutative
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{ X86::FpSUB, X86::FSUBRST0r },
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{ X86::FpUCOM, ~0 },
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};
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// ForwardSTiTable - Map: A = B op C into: ST(i) = ST(0) op ST(i)
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static const TableEntry ForwardSTiTable[] = {
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{ X86::FpADD, X86::FADDrST0 }, // commutative
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{ X86::FpDIV, X86::FDIVRrST0 },
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{ X86::FpMUL, X86::FMULrST0 }, // commutative
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{ X86::FpSUB, X86::FSUBRrST0 },
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{ X86::FpUCOM, X86::FUCOMr },
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};
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// ReverseSTiTable - Map: A = B op C into: ST(i) = ST(i) op ST(0)
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static const TableEntry ReverseSTiTable[] = {
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{ X86::FpADD, X86::FADDrST0 },
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{ X86::FpDIV, X86::FDIVrST0 },
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{ X86::FpMUL, X86::FMULrST0 },
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{ X86::FpSUB, X86::FSUBrST0 },
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{ X86::FpUCOM, ~0 },
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};
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/// handleTwoArgFP - Handle instructions like FADD and friends which are virtual
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/// instructions which need to be simplified and possibly transformed.
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///
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/// Result: ST(0) = fsub ST(0), ST(i)
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/// ST(i) = fsub ST(0), ST(i)
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/// ST(0) = fsubr ST(0), ST(i)
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/// ST(i) = fsubr ST(0), ST(i)
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///
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/// In addition to three address instructions, this also handles the FpUCOM
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/// instruction which only has two operands, but no destination. This
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/// instruction is also annoying because there is no "reverse" form of it
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/// available.
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///
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void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
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ASSERT_SORTED(ForwardST0Table); ASSERT_SORTED(ReverseST0Table);
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ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
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MachineInstr *MI = *I;
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unsigned NumOperands = MI->getNumOperands();
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assert(NumOperands == 3 ||
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(NumOperands == 2 && MI->getOpcode() == X86::FpUCOM) &&
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"Illegal TwoArgFP instruction!");
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unsigned Dest = getFPReg(MI->getOperand(0));
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unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
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unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
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bool KillsOp0 = false, KillsOp1 = false;
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for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
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E = LV->killed_end(MI); KI != E; ++KI) {
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KillsOp0 |= (KI->second == X86::FP0+Op0);
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KillsOp1 |= (KI->second == X86::FP0+Op1);
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}
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// If this is an FpUCOM instruction, we must make sure the first operand is on
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// the top of stack, the other one can be anywhere...
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if (MI->getOpcode() == X86::FpUCOM)
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moveToTop(Op0, I);
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unsigned TOS = getStackEntry(0);
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// One of our operands must be on the top of the stack. If neither is yet, we
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// need to move one.
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if (Op0 != TOS && Op1 != TOS) { // No operand at TOS?
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|
// We can choose to move either operand to the top of the stack. If one of
|
|
// the operands is killed by this instruction, we want that one so that we
|
|
// can update right on top of the old version.
|
|
if (KillsOp0) {
|
|
moveToTop(Op0, I); // Move dead operand to TOS.
|
|
TOS = Op0;
|
|
} else if (KillsOp1) {
|
|
moveToTop(Op1, I);
|
|
TOS = Op1;
|
|
} else {
|
|
// All of the operands are live after this instruction executes, so we
|
|
// cannot update on top of any operand. Because of this, we must
|
|
// duplicate one of the stack elements to the top. It doesn't matter
|
|
// which one we pick.
|
|
//
|
|
duplicateToTop(Op0, Dest, I);
|
|
Op0 = TOS = Dest;
|
|
KillsOp0 = true;
|
|
}
|
|
} else if (!KillsOp0 && !KillsOp1 && MI->getOpcode() != X86::FpUCOM) {
|
|
// If we DO have one of our operands at the top of the stack, but we don't
|
|
// have a dead operand, we must duplicate one of the operands to a new slot
|
|
// on the stack.
|
|
duplicateToTop(Op0, Dest, I);
|
|
Op0 = TOS = Dest;
|
|
KillsOp0 = true;
|
|
}
|
|
|
|
// Now we know that one of our operands is on the top of the stack, and at
|
|
// least one of our operands is killed by this instruction.
|
|
assert((TOS == Op0 || TOS == Op1) &&
|
|
(KillsOp0 || KillsOp1 || MI->getOpcode() == X86::FpUCOM) &&
|
|
"Stack conditions not set up right!");
|
|
|
|
// We decide which form to use based on what is on the top of the stack, and
|
|
// which operand is killed by this instruction.
|
|
const TableEntry *InstTable;
|
|
bool isForward = TOS == Op0;
|
|
bool updateST0 = (TOS == Op0 && !KillsOp1) || (TOS == Op1 && !KillsOp0);
|
|
if (updateST0) {
|
|
if (isForward)
|
|
InstTable = ForwardST0Table;
|
|
else
|
|
InstTable = ReverseST0Table;
|
|
} else {
|
|
if (isForward)
|
|
InstTable = ForwardSTiTable;
|
|
else
|
|
InstTable = ReverseSTiTable;
|
|
}
|
|
|
|
int Opcode = Lookup(InstTable, ARRAY_SIZE(ForwardST0Table), MI->getOpcode());
|
|
assert(Opcode != -1 && "Unknown TwoArgFP pseudo instruction!");
|
|
|
|
// NotTOS - The register which is not on the top of stack...
|
|
unsigned NotTOS = (TOS == Op0) ? Op1 : Op0;
|
|
|
|
// Replace the old instruction with a new instruction
|
|
*I = BuildMI(Opcode, 1).addReg(getSTReg(NotTOS));
|
|
|
|
// If both operands are killed, pop one off of the stack in addition to
|
|
// overwriting the other one.
|
|
if (KillsOp0 && KillsOp1 && Op0 != Op1) {
|
|
assert(!updateST0 && "Should have updated other operand!");
|
|
popStackAfter(I); // Pop the top of stack
|
|
}
|
|
|
|
// Insert an explicit pop of the "updated" operand for FUCOM
|
|
if (MI->getOpcode() == X86::FpUCOM) {
|
|
if (KillsOp0 && !KillsOp1)
|
|
popStackAfter(I); // If we kill the first operand, pop it!
|
|
else if (KillsOp1 && Op0 != Op1) {
|
|
if (getStackEntry(0) == Op1) {
|
|
popStackAfter(I); // If it's right at the top of stack, just pop it
|
|
} else {
|
|
// Otherwise, move the top of stack into the dead slot, killing the
|
|
// operand without having to add in an explicit xchg then pop.
|
|
//
|
|
unsigned STReg = getSTReg(Op1);
|
|
unsigned OldSlot = getSlot(Op1);
|
|
unsigned TopReg = Stack[StackTop-1];
|
|
Stack[OldSlot] = TopReg;
|
|
RegMap[TopReg] = OldSlot;
|
|
RegMap[Op1] = ~0;
|
|
Stack[--StackTop] = ~0;
|
|
|
|
MachineInstr *MI = BuildMI(X86::FSTPrr, 1).addReg(STReg);
|
|
I = MBB->insert(I+1, MI);
|
|
}
|
|
}
|
|
}
|
|
|
|
// Update stack information so that we know the destination register is now on
|
|
// the stack.
|
|
if (MI->getOpcode() != X86::FpUCOM) {
|
|
unsigned UpdatedSlot = getSlot(updateST0 ? TOS : NotTOS);
|
|
assert(UpdatedSlot < StackTop && Dest < 7);
|
|
Stack[UpdatedSlot] = Dest;
|
|
RegMap[Dest] = UpdatedSlot;
|
|
}
|
|
delete MI; // Remove the old instruction
|
|
}
|
|
|
|
|
|
/// handleSpecialFP - Handle special instructions which behave unlike other
|
|
/// floating point instructions. This is primarily intended for use by pseudo
|
|
/// instructions.
|
|
///
|
|
void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) {
|
|
MachineInstr *MI = *I;
|
|
switch (MI->getOpcode()) {
|
|
default: assert(0 && "Unknown SpecialFP instruction!");
|
|
case X86::FpGETRESULT: // Appears immediately after a call returning FP type!
|
|
assert(StackTop == 0 && "Stack should be empty after a call!");
|
|
pushReg(getFPReg(MI->getOperand(0)));
|
|
break;
|
|
case X86::FpSETRESULT:
|
|
assert(StackTop == 1 && "Stack should have one element on it to return!");
|
|
--StackTop; // "Forget" we have something on the top of stack!
|
|
break;
|
|
case X86::FpMOV: {
|
|
unsigned SrcReg = getFPReg(MI->getOperand(1));
|
|
unsigned DestReg = getFPReg(MI->getOperand(0));
|
|
bool KillsSrc = false;
|
|
for (LiveVariables::killed_iterator KI = LV->killed_begin(MI),
|
|
E = LV->killed_end(MI); KI != E; ++KI)
|
|
KillsSrc |= KI->second == X86::FP0+SrcReg;
|
|
|
|
if (KillsSrc) {
|
|
// If the input operand is killed, we can just change the owner of the
|
|
// incoming stack slot into the result.
|
|
unsigned Slot = getSlot(SrcReg);
|
|
assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!");
|
|
Stack[Slot] = DestReg;
|
|
RegMap[DestReg] = Slot;
|
|
|
|
} else {
|
|
// For FMOV we just duplicate the specified value to a new stack slot.
|
|
// This could be made better, but would require substantial changes.
|
|
duplicateToTop(SrcReg, DestReg, I);
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
|
|
I = MBB->erase(I)-1; // Remove the pseudo instruction
|
|
}
|
|
|
|
namespace {
|
|
|
|
struct FPK : public MachineFunctionPass {
|
|
virtual const char *getPassName() const { return "X86 FP Killer"; }
|
|
virtual bool runOnMachineFunction(MachineFunction &MF);
|
|
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
|
|
AU.setPreservesAll();
|
|
AU.addRequired<LiveVariables>();
|
|
AU.addRequiredID(PHIEliminationID);
|
|
MachineFunctionPass::getAnalysisUsage(AU);
|
|
}
|
|
};
|
|
}
|
|
|
|
FunctionPass * createX86FloatingPointKillerPass() { return new FPK(); }
|
|
|
|
bool FPK::runOnMachineFunction(MachineFunction &MF)
|
|
{
|
|
const TargetInstrInfo& tii = MF.getTarget().getInstrInfo();;
|
|
|
|
for (MachineFunction::iterator
|
|
mbbi = MF.begin(), mbbe = MF.end(); mbbi != mbbe; ++mbbi) {
|
|
MachineBasicBlock& mbb = *mbbi;
|
|
MachineBasicBlock::reverse_iterator mii = mbb.rbegin();
|
|
// rewind to the last non terminating instruction
|
|
while (mii != mbb.rend() && tii.isTerminatorInstr((*mii)->getOpcode())) {
|
|
++mii;
|
|
}
|
|
// add implicit def for all virtual floating point registers so that
|
|
// they are spilled at the end of each basic block, since our
|
|
// register stackifier doesn't handle them otherwise.
|
|
MachineInstr* instr = BuildMI(X86::IMPLICIT_DEF, 7)
|
|
.addReg(X86::FP6, MOTy::Def)
|
|
.addReg(X86::FP5, MOTy::Def)
|
|
.addReg(X86::FP4, MOTy::Def)
|
|
.addReg(X86::FP3, MOTy::Def)
|
|
.addReg(X86::FP2, MOTy::Def)
|
|
.addReg(X86::FP1, MOTy::Def)
|
|
.addReg(X86::FP0, MOTy::Def);
|
|
|
|
mbb.insert(mii.base(), instr);
|
|
LiveVariables& lv = getAnalysis<LiveVariables>();
|
|
for (unsigned i = 0; i < instr->getNumOperands(); ++i) {
|
|
lv.HandlePhysRegDef(instr->getOperand(i).getAllocatedRegNum(), instr);
|
|
// force live variables to compute that these registers are dead
|
|
lv.HandlePhysRegDef(instr->getOperand(i).getAllocatedRegNum(), 0);
|
|
}
|
|
}
|
|
return true;
|
|
}
|
|
|
|
} // End llvm namespace
|