mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 20:29:48 +00:00
37fe6627f6
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205884 91177308-0d34-0410-b5e6-96231b3b80d8
239 lines
8.4 KiB
LLVM
239 lines
8.4 KiB
LLVM
; RUN: llc < %s -march=arm64 -mcpu=cyclone -enable-misched=false | FileCheck %s
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; RUN: llc < %s -O0 | FileCheck -check-prefix=FAST %s
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target triple = "arm64-apple-darwin"
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; rdar://9932559
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define i64 @i8i16callee(i64 %a1, i64 %a2, i64 %a3, i8 signext %a4, i16 signext %a5, i64 %a6, i64 %a7, i64 %a8, i8 signext %b1, i16 signext %b2, i8 signext %b3, i8 signext %b4) nounwind readnone noinline {
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entry:
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; CHECK-LABEL: i8i16callee:
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; The 8th, 9th, 10th and 11th arguments are passed at sp, sp+2, sp+4, sp+5.
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; They are i8, i16, i8 and i8.
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; CHECK: ldrsb {{w[0-9]+}}, [sp, #5]
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; CHECK: ldrsh {{w[0-9]+}}, [sp, #2]
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; CHECK: ldrsb {{w[0-9]+}}, [sp]
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; CHECK: ldrsb {{w[0-9]+}}, [sp, #4]
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; FAST-LABEL: i8i16callee:
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; FAST: ldrb {{w[0-9]+}}, [sp, #5]
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; FAST: ldrb {{w[0-9]+}}, [sp, #4]
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; FAST: ldrh {{w[0-9]+}}, [sp, #2]
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; FAST: ldrb {{w[0-9]+}}, [sp]
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%conv = sext i8 %a4 to i64
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%conv3 = sext i16 %a5 to i64
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%conv8 = sext i8 %b1 to i64
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%conv9 = sext i16 %b2 to i64
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%conv11 = sext i8 %b3 to i64
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%conv13 = sext i8 %b4 to i64
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%add10 = add i64 %a2, %a1
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%add12 = add i64 %add10, %a3
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%add14 = add i64 %add12, %conv
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%add = add i64 %add14, %conv3
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%add1 = add i64 %add, %a6
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%add2 = add i64 %add1, %a7
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%add4 = add i64 %add2, %a8
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%add5 = add i64 %add4, %conv8
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%add6 = add i64 %add5, %conv9
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%add7 = add i64 %add6, %conv11
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%add15 = add i64 %add7, %conv13
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%sext = shl i64 %add15, 32
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%conv17 = ashr exact i64 %sext, 32
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ret i64 %conv17
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}
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define i32 @i8i16caller() nounwind readnone {
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entry:
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; CHECK: i8i16caller
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; The 8th, 9th, 10th and 11th arguments are passed at sp, sp+2, sp+4, sp+5.
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; They are i8, i16, i8 and i8.
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; CHECK: strb {{w[0-9]+}}, [sp, #5]
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; CHECK: strb {{w[0-9]+}}, [sp, #4]
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; CHECK: strh {{w[0-9]+}}, [sp, #2]
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; CHECK: strb {{w[0-9]+}}, [sp]
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; CHECK: bl
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; FAST: i8i16caller
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; FAST: strb {{w[0-9]+}}, [sp]
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; FAST: strh {{w[0-9]+}}, [sp, #2]
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; FAST: strb {{w[0-9]+}}, [sp, #4]
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; FAST: strb {{w[0-9]+}}, [sp, #5]
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; FAST: bl
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%call = tail call i64 @i8i16callee(i64 0, i64 1, i64 2, i8 signext 3, i16 signext 4, i64 5, i64 6, i64 7, i8 signext 97, i16 signext 98, i8 signext 99, i8 signext 100)
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%conv = trunc i64 %call to i32
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ret i32 %conv
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}
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; rdar://12651543
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define double @circle_center([2 x float] %a) nounwind ssp {
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%call = tail call double @ext([2 x float] %a) nounwind
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; CHECK: circle_center
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; CHECK: bl
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ret double %call
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}
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declare double @ext([2 x float])
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; rdar://12656141
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; 16-byte vector should be aligned at 16-byte when passing on stack.
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; A double argument will be passed on stack, so vecotr should be at sp+16.
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define double @fixed_4i(<4 x i32>* nocapture %in) nounwind {
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entry:
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; CHECK: fixed_4i
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; CHECK: str [[REG_1:q[0-9]+]], [sp, #16]
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; FAST: fixed_4i
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; FAST: sub sp, sp, #64
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; FAST: mov x[[ADDR:[0-9]+]], sp
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; FAST: str [[REG_1:q[0-9]+]], [x[[ADDR]], #16]
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%0 = load <4 x i32>* %in, align 16
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%call = tail call double @args_vec_4i(double 3.000000e+00, <4 x i32> %0, <4 x i32> %0, <4 x i32> %0, <4 x i32> %0, <4 x i32> %0, <4 x i32> %0, <4 x i32> %0, double 3.000000e+00, <4 x i32> %0, i8 signext 3)
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ret double %call
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}
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declare double @args_vec_4i(double, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, double, <4 x i32>, i8 signext)
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; rdar://12695237
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; d8 at sp, i in register w0.
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@g_d = common global double 0.000000e+00, align 8
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define void @test1(float %f1, double %d1, double %d2, double %d3, double %d4,
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double %d5, double %d6, double %d7, double %d8, i32 %i) nounwind ssp {
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entry:
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; CHECK: test1
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; CHECK: ldr [[REG_1:d[0-9]+]], [sp]
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; CHECK: scvtf [[REG_2:s[0-9]+]], w0
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; CHECK: fadd s0, [[REG_2]], s0
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%conv = sitofp i32 %i to float
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%add = fadd float %conv, %f1
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%conv1 = fpext float %add to double
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%add2 = fadd double %conv1, %d7
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%add3 = fadd double %add2, %d8
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store double %add3, double* @g_d, align 8
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ret void
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}
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; i9 at sp, d1 in register s0.
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define void @test2(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6,
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i32 %i7, i32 %i8, i32 %i9, float %d1) nounwind ssp {
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entry:
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; CHECK: test2
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; CHECK: scvtf [[REG_2:s[0-9]+]], w0
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; CHECK: fadd s0, [[REG_2]], s0
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; CHECK: ldr [[REG_1:s[0-9]+]], [sp]
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%conv = sitofp i32 %i1 to float
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%add = fadd float %conv, %d1
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%conv1 = fpext float %add to double
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%conv2 = sitofp i32 %i8 to double
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%add3 = fadd double %conv2, %conv1
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%conv4 = sitofp i32 %i9 to double
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%add5 = fadd double %conv4, %add3
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store double %add5, double* @g_d, align 8
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ret void
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}
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; rdar://12648441
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; Check alignment on stack for v64, f64, i64, f32, i32.
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define double @test3(<2 x i32>* nocapture %in) nounwind {
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entry:
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; CHECK: test3
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; CHECK: str [[REG_1:d[0-9]+]], [sp, #8]
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; FAST: test3
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; FAST: sub sp, sp, #32
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; FAST: mov x[[ADDR:[0-9]+]], sp
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; FAST: str [[REG_1:d[0-9]+]], [x[[ADDR]], #8]
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%0 = load <2 x i32>* %in, align 8
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%call = tail call double @args_vec_2i(double 3.000000e+00, <2 x i32> %0,
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<2 x i32> %0, <2 x i32> %0, <2 x i32> %0, <2 x i32> %0, <2 x i32> %0,
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<2 x i32> %0, float 3.000000e+00, <2 x i32> %0, i8 signext 3)
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ret double %call
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}
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declare double @args_vec_2i(double, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>,
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<2 x i32>, <2 x i32>, <2 x i32>, float, <2 x i32>, i8 signext)
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define double @test4(double* nocapture %in) nounwind {
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entry:
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; CHECK: test4
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; CHECK: str [[REG_1:d[0-9]+]], [sp, #8]
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; CHECK: str [[REG_2:w[0-9]+]], [sp]
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; CHECK: orr w0, wzr, #0x3
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%0 = load double* %in, align 8
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%call = tail call double @args_f64(double 3.000000e+00, double %0, double %0,
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double %0, double %0, double %0, double %0, double %0,
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float 3.000000e+00, double %0, i8 signext 3)
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ret double %call
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}
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declare double @args_f64(double, double, double, double, double, double, double,
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double, float, double, i8 signext)
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define i64 @test5(i64* nocapture %in) nounwind {
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entry:
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; CHECK: test5
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; CHECK: strb [[REG_3:w[0-9]+]], [sp, #16]
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; CHECK: str [[REG_1:x[0-9]+]], [sp, #8]
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; CHECK: str [[REG_2:w[0-9]+]], [sp]
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%0 = load i64* %in, align 8
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%call = tail call i64 @args_i64(i64 3, i64 %0, i64 %0, i64 %0, i64 %0, i64 %0,
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i64 %0, i64 %0, i32 3, i64 %0, i8 signext 3)
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ret i64 %call
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}
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declare i64 @args_i64(i64, i64, i64, i64, i64, i64, i64, i64, i32, i64,
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i8 signext)
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define i32 @test6(float* nocapture %in) nounwind {
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entry:
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; CHECK: test6
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; CHECK: strb [[REG_2:w[0-9]+]], [sp, #8]
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; CHECK: str [[REG_1:s[0-9]+]], [sp, #4]
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; CHECK: strh [[REG_3:w[0-9]+]], [sp]
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%0 = load float* %in, align 4
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%call = tail call i32 @args_f32(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6,
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i32 7, i32 8, float 1.0, float 2.0, float 3.0, float 4.0, float 5.0,
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float 6.0, float 7.0, float 8.0, i16 signext 3, float %0,
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i8 signext 3)
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ret i32 %call
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}
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declare i32 @args_f32(i32, i32, i32, i32, i32, i32, i32, i32,
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float, float, float, float, float, float, float, float,
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i16 signext, float, i8 signext)
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define i32 @test7(i32* nocapture %in) nounwind {
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entry:
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; CHECK: test7
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; CHECK: strb [[REG_2:w[0-9]+]], [sp, #8]
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; CHECK: str [[REG_1:w[0-9]+]], [sp, #4]
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; CHECK: strh [[REG_3:w[0-9]+]], [sp]
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%0 = load i32* %in, align 4
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%call = tail call i32 @args_i32(i32 3, i32 %0, i32 %0, i32 %0, i32 %0, i32 %0,
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i32 %0, i32 %0, i16 signext 3, i32 %0, i8 signext 4)
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ret i32 %call
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}
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declare i32 @args_i32(i32, i32, i32, i32, i32, i32, i32, i32, i16 signext, i32,
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i8 signext)
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define i32 @test8(i32 %argc, i8** nocapture %argv) nounwind {
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entry:
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; CHECK: test8
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; CHECK: strb {{w[0-9]+}}, [sp, #3]
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; CHECK: strb wzr, [sp, #2]
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; CHECK: strb {{w[0-9]+}}, [sp, #1]
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; CHECK: strb wzr, [sp]
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; CHECK: bl
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; FAST: test8
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; FAST: strb {{w[0-9]+}}, [sp]
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; FAST: strb {{w[0-9]+}}, [sp, #1]
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; FAST: strb {{w[0-9]+}}, [sp, #2]
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; FAST: strb {{w[0-9]+}}, [sp, #3]
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; FAST: bl
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tail call void @args_i1(i1 zeroext false, i1 zeroext true, i1 zeroext false,
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i1 zeroext true, i1 zeroext false, i1 zeroext true,
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i1 zeroext false, i1 zeroext true, i1 zeroext false,
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i1 zeroext true, i1 zeroext false, i1 zeroext true)
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ret i32 0
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}
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declare void @args_i1(i1 zeroext, i1 zeroext, i1 zeroext, i1 zeroext,
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i1 zeroext, i1 zeroext, i1 zeroext, i1 zeroext,
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i1 zeroext, i1 zeroext, i1 zeroext, i1 zeroext)
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define i32 @i1_stack_incoming(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f,
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i64 %g, i64 %h, i64 %i, i1 zeroext %j) {
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; CHECK-LABEL: i1_stack_incoming:
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; CHECK: ldrb w0, [sp, #8]
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; CHECK: ret
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%v = zext i1 %j to i32
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ret i32 %v
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}
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