llvm-6502/test/CodeGen/ARM64/convert-v2i32-v2f64.ll
Tim Northover 7b837d8c75 ARM64: initial backend import
This adds a second implementation of the AArch64 architecture to LLVM,
accessible in parallel via the "arm64" triple. The plan over the
coming weeks & months is to merge the two into a single backend,
during which time thorough code review should naturally occur.

Everything will be easier with the target in-tree though, hence this
commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-29 10:18:08 +00:00

30 lines
742 B
LLVM

; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple | FileCheck %s
define <2 x double> @f1(<2 x i32> %v) nounwind readnone {
; CHECK-LABEL: f1:
; CHECK: sshll.2d v0, v0, #0
; CHECK-NEXT: scvtf.2d v0, v0
; CHECK-NEXT: ret
%conv = sitofp <2 x i32> %v to <2 x double>
ret <2 x double> %conv
}
define <2 x double> @f2(<2 x i32> %v) nounwind readnone {
; CHECK-LABEL: f2:
; CHECK: ushll.2d v0, v0, #0
; CHECK-NEXT: ucvtf.2d v0, v0
; CHECK-NEXT: ret
%conv = uitofp <2 x i32> %v to <2 x double>
ret <2 x double> %conv
}
; CHECK: autogen_SD19655
; CHECK: scvtf
; CHECK: ret
define void @autogen_SD19655() {
%T = load <2 x i64>* undef
%F = sitofp <2 x i64> undef to <2 x float>
store <2 x float> %F, <2 x float>* undef
ret void
}