Jim Grosbach b54efe809f ARM 'adr' fixups don't need the interworking addend tweaking. ... They reference the PC directly, so things work properly that way. rdar://11231229 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154576 91177308-0d34-0410-b5e6-96231b3b80d8		2012-04-12 01:19:35 +00:00
..
ARMAddressingModes.h	Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.	2012-02-18 12:03:15 +00:00
ARMAsmBackend.cpp	ARM 'adr' fixups don't need the interworking addend tweaking.	2012-04-12 01:19:35 +00:00
ARMBaseInfo.h	ARM more NEON VLD/VST composite physical register refactoring.	2012-03-06 23:10:38 +00:00
ARMELFObjectWriter.cpp	Ensure conditional BL instructions for ARM are given the fixup fixup_arm_condbranch.	2012-03-30 09:15:32 +00:00
ARMFixupKinds.h	Ensure conditional BL instructions for ARM are given the fixup fixup_arm_condbranch.	2012-03-30 09:15:32 +00:00
ARMMachObjectWriter.cpp	Ensure conditional BL instructions for ARM are given the fixup fixup_arm_condbranch.	2012-03-30 09:15:32 +00:00
ARMMCAsmInfo.cpp	Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.	2012-02-18 12:03:15 +00:00
ARMMCAsmInfo.h	Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.	2012-02-18 12:03:15 +00:00
ARMMCCodeEmitter.cpp	Ensure conditional BL instructions for ARM are given the fixup fixup_arm_condbranch.	2012-03-30 09:15:32 +00:00
ARMMCExpr.cpp
ARMMCExpr.h	Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.	2012-02-18 12:03:15 +00:00
ARMMCTargetDesc.cpp	Make MCInstrInfo available to the MCInstPrinter. This will be used to remove getInstructionName and the static data it contains since the same tables are already in MCInstrInfo.	2012-04-02 06:09:36 +00:00
ARMMCTargetDesc.h
CMakeLists.txt
LLVMBuild.txt
Makefile