Andrea Di Biagio 36280bde58 Update test/CodeGen/X86/vbinop-simplify-bug.ll. ... Redirect the output of llc to /dev/null. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199329 91177308-0d34-0410-b5e6-96231b3b80d8		2014-01-15 20:16:14 +00:00
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AArch64	For AArch64, lowering sext_inreg and generate optimized code by using SXTL.	2014-01-15 05:08:01 +00:00
ARM	PR 18466: Fix ARM Pseudo Expansion	2014-01-15 01:32:12 +00:00
CPP	Begin adding docs and IR-level support for the inalloca attribute	2013-12-19 02:14:12 +00:00
Generic	Remove a failing test to get the buildbots back to green.	2014-01-06 00:43:09 +00:00
Hexagon	Debug Info: update testing cases to specify the debug info version number.	2013-11-22 21:49:45 +00:00
Inputs	Debug Info: update testing cases to specify the debug info version number.	2013-11-22 21:49:45 +00:00
Mips	Fix a low hanging use of hasRawTextSupport.	2014-01-14 18:57:12 +00:00
MSP430	Make sure SP is always aligned on a 2 byte boundary	2013-10-24 09:32:31 +00:00
NVPTX	Fix non-deterministic SDNodeOrder-dependent codegen	2014-01-12 14:09:17 +00:00
PowerPC	Implement initial-exec TLS for PPC32.	2013-12-20 18:08:54 +00:00
R600	Fix broken CHECK lines.	2014-01-11 21:06:00 +00:00
SPARC	Always let value types influence register classes.	2014-01-14 06:18:38 +00:00
SystemZ	[SystemZ] Flesh out stackrestore test (frame-11.ll)	2014-01-13 15:44:44 +00:00
Thumb	Fix broken CHECK lines.	2014-01-11 21:06:00 +00:00
Thumb2	Fix PR 18369: [Thumbv8] asserts due to inconsistent CPSR liveness of IT blocks	2014-01-13 18:47:54 +00:00
X86	Update test/CodeGen/X86/vbinop-simplify-bug.ll.	2014-01-15 20:16:14 +00:00
XCore	Fix broken CHECK lines.	2014-01-11 21:06:00 +00:00