llvm-6502/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt
Johnny Chen 103bf951a4 Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000.
rdar://problem/9224276


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128749 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-01 23:30:25 +00:00

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# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
# Opcode=0 Name=PHI Format=(42)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 1: 0|
# -------------------------------------------------------------------------------------------------
# To qualify as a MOV (register) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100.
# The instruction is UNPREDICTABLE, and is not a valid intruction.
#
# See also
# A8.6.97 MOV (register)
0x2 0xd0 0xbc 0xf1