mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-03 02:30:00 +00:00
7b837d8c75
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205090 91177308-0d34-0410-b5e6-96231b3b80d8
110 lines
3.5 KiB
LLVM
110 lines
3.5 KiB
LLVM
; RUN: llc -march=arm64 -arm64-neon-syntax=apple < %s | FileCheck %s
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define <8 x i8> @test_vclz_u8(<8 x i8> %a) nounwind readnone ssp {
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; CHECK-LABEL: test_vclz_u8:
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; CHECK: clz.8b v0, v0
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; CHECK-NEXT: ret
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%vclz.i = tail call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %a, i1 false) nounwind
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ret <8 x i8> %vclz.i
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}
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define <8 x i8> @test_vclz_s8(<8 x i8> %a) nounwind readnone ssp {
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; CHECK-LABEL: test_vclz_s8:
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; CHECK: clz.8b v0, v0
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; CHECK-NEXT: ret
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%vclz.i = tail call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %a, i1 false) nounwind
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ret <8 x i8> %vclz.i
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}
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define <4 x i16> @test_vclz_u16(<4 x i16> %a) nounwind readnone ssp {
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; CHECK-LABEL: test_vclz_u16:
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; CHECK: clz.4h v0, v0
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; CHECK-NEXT: ret
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%vclz1.i = tail call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %a, i1 false) nounwind
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ret <4 x i16> %vclz1.i
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}
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define <4 x i16> @test_vclz_s16(<4 x i16> %a) nounwind readnone ssp {
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; CHECK-LABEL: test_vclz_s16:
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; CHECK: clz.4h v0, v0
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; CHECK-NEXT: ret
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%vclz1.i = tail call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %a, i1 false) nounwind
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ret <4 x i16> %vclz1.i
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}
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define <2 x i32> @test_vclz_u32(<2 x i32> %a) nounwind readnone ssp {
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; CHECK-LABEL: test_vclz_u32:
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; CHECK: clz.2s v0, v0
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; CHECK-NEXT: ret
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%vclz1.i = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %a, i1 false) nounwind
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ret <2 x i32> %vclz1.i
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}
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define <2 x i32> @test_vclz_s32(<2 x i32> %a) nounwind readnone ssp {
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; CHECK-LABEL: test_vclz_s32:
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; CHECK: clz.2s v0, v0
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; CHECK-NEXT: ret
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%vclz1.i = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %a, i1 false) nounwind
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ret <2 x i32> %vclz1.i
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}
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define <16 x i8> @test_vclzq_u8(<16 x i8> %a) nounwind readnone ssp {
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; CHECK-LABEL: test_vclzq_u8:
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; CHECK: clz.16b v0, v0
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; CHECK-NEXT: ret
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%vclz.i = tail call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %a, i1 false) nounwind
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ret <16 x i8> %vclz.i
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}
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define <16 x i8> @test_vclzq_s8(<16 x i8> %a) nounwind readnone ssp {
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; CHECK-LABEL: test_vclzq_s8:
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; CHECK: clz.16b v0, v0
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; CHECK-NEXT: ret
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%vclz.i = tail call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %a, i1 false) nounwind
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ret <16 x i8> %vclz.i
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}
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define <8 x i16> @test_vclzq_u16(<8 x i16> %a) nounwind readnone ssp {
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; CHECK-LABEL: test_vclzq_u16:
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; CHECK: clz.8h v0, v0
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; CHECK-NEXT: ret
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%vclz1.i = tail call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %a, i1 false) nounwind
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ret <8 x i16> %vclz1.i
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}
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define <8 x i16> @test_vclzq_s16(<8 x i16> %a) nounwind readnone ssp {
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; CHECK-LABEL: test_vclzq_s16:
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; CHECK: clz.8h v0, v0
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; CHECK-NEXT: ret
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%vclz1.i = tail call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %a, i1 false) nounwind
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ret <8 x i16> %vclz1.i
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}
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define <4 x i32> @test_vclzq_u32(<4 x i32> %a) nounwind readnone ssp {
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; CHECK-LABEL: test_vclzq_u32:
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; CHECK: clz.4s v0, v0
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; CHECK-NEXT: ret
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%vclz1.i = tail call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %a, i1 false) nounwind
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ret <4 x i32> %vclz1.i
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}
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define <4 x i32> @test_vclzq_s32(<4 x i32> %a) nounwind readnone ssp {
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; CHECK-LABEL: test_vclzq_s32:
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; CHECK: clz.4s v0, v0
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; CHECK-NEXT: ret
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%vclz1.i = tail call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %a, i1 false) nounwind
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ret <4 x i32> %vclz1.i
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}
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declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone
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declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1) nounwind readnone
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declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>, i1) nounwind readnone
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declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1) nounwind readnone
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declare <4 x i16> @llvm.ctlz.v4i16(<4 x i16>, i1) nounwind readnone
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declare <8 x i8> @llvm.ctlz.v8i8(<8 x i8>, i1) nounwind readnone
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