Igor Breger 368de4c9d6 AVX : Fix ISA disabling in case AVX512VL , some instructions should be disabled only if AVX512BW present. ... Tests added. Differential Revision: http://reviews.llvm.org/D11122 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242270 91177308-0d34-0410-b5e6-96231b3b80d8		2015-07-15 07:08:10 +00:00
..
AArch64	WebAssembly: fix build breakage.	2015-07-14 23:06:07 +00:00
AMDGPU	AMDGPU: Avoid using 64-bit shift for i64 (shl x, 32)	2015-07-14 18:20:33 +00:00
ARM	ARM: add at least one real test for r242123.	2015-07-14 17:23:55 +00:00
BPF
CPP
Generic
Hexagon	[Hexagon] Generate instructions for operations on predicate registers	2015-07-14 19:30:21 +00:00
Inputs
Mips
MIR	MIR Serialization: Serialize the machine basic block live in registers.	2015-07-14 21:24:41 +00:00
MSP430
NVPTX	Actually support volatile memcpys in NVPTX lowering	2015-07-10 15:40:33 +00:00
PowerPC	[PowerPC] Support symbolic targets in patchpoints	2015-07-14 22:53:11 +00:00
SPARC
SystemZ
Thumb
Thumb2	Revert "LegalizeDAG: Fix and improve FCOPYSIGN/FABS legalization"	2015-07-14 02:09:57 +00:00
WebAssembly
WinEH	[WinEH] Strip the \01 character from the __CxxFrameHandler3 thunk name	2015-07-13 17:55:14 +00:00
X86	AVX : Fix ISA disabling in case AVX512VL , some instructions should be disabled only if AVX512BW present.	2015-07-15 07:08:10 +00:00
XCore