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Generate code for the Blackfin family of DSPs from Analog Devices: http://www.analog.com/en/embedded-processing-dsp/blackfin/processors/index.html We aim to be compatible with the exsisting GNU toolchain found at: http://blackfin.uclinux.org/gf/project/toolchain The back-end is experimental. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77897 91177308-0d34-0410-b5e6-96231b3b80d8
52 lines
956 B
LLVM
52 lines
956 B
LLVM
; RUN: llvm-as < %s | llc -march=bfin -verify-machineinstrs
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define i64 @add(i64 %A, i64 %B) {
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%R = add i64 %A, %B ; <i64> [#uses=1]
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ret i64 %R
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}
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define i64 @sub(i64 %A, i64 %B) {
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%R = sub i64 %A, %B ; <i64> [#uses=1]
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ret i64 %R
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}
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define i64 @mul(i64 %A, i64 %B) {
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%R = mul i64 %A, %B ; <i64> [#uses=1]
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ret i64 %R
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}
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define i64 @sdiv(i64 %A, i64 %B) {
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%R = sdiv i64 %A, %B ; <i64> [#uses=1]
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ret i64 %R
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}
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define i64 @udiv(i64 %A, i64 %B) {
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%R = udiv i64 %A, %B ; <i64> [#uses=1]
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ret i64 %R
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}
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define i64 @srem(i64 %A, i64 %B) {
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%R = srem i64 %A, %B ; <i64> [#uses=1]
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ret i64 %R
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}
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define i64 @urem(i64 %A, i64 %B) {
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%R = urem i64 %A, %B ; <i64> [#uses=1]
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ret i64 %R
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}
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define i64 @and(i64 %A, i64 %B) {
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%R = and i64 %A, %B ; <i64> [#uses=1]
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ret i64 %R
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}
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define i64 @or(i64 %A, i64 %B) {
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%R = or i64 %A, %B ; <i64> [#uses=1]
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ret i64 %R
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}
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define i64 @xor(i64 %A, i64 %B) {
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%R = xor i64 %A, %B ; <i64> [#uses=1]
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ret i64 %R
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}
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