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f8d179ba76
This adds support for the QPX vector instruction set, which is used by the
enhanced A2 cores on the IBM BG/Q supercomputers. QPX vectors are 256 bytes
wide, holding 4 double-precision floating-point values. Boolean values, modeled
here as <4 x i1> are actually also represented as floating-point values
(essentially { -1, 1 } for { false, true }). QPX shares many features with
Altivec and VSX, but is distinct from both of them. One major difference is
that, instead of adding completely-separate vector registers, QPX vector
registers are extensions of the scalar floating-point registers (lane 0 is the
corresponding scalar floating-point value). The operations supported on QPX
vectors mirrors that supported on the scalar floating-point values (with some
additional ones for permutations and logical/comparison operations).
I've been maintaining this support out-of-tree, as part of the bgclang project,
for several years. This is not the entire bgclang patch set, but is most of the
subset that can be cleanly integrated into LLVM proper at this time. Adding
this to the LLVM backend is part of my efforts to rebase bgclang to the current
LLVM trunk, but is independently useful (especially for codes that use LLVM as
a JIT in library form).
The assembler/disassembler test coverage is complete. The CodeGen test coverage
is not, but I've included some tests, and more will be added as follow-up work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230413 91177308-0d34-0410-b5e6-96231b3b80d8
261 lines
12 KiB
TableGen
261 lines
12 KiB
TableGen
//===- PPCCallingConv.td - Calling Conventions for PowerPC -*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This describes the calling conventions for the PowerPC 32- and 64-bit
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// architectures.
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//
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//===----------------------------------------------------------------------===//
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/// CCIfSubtarget - Match if the current subtarget has a feature F.
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class CCIfSubtarget<string F, CCAction A>
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: CCIf<!strconcat("static_cast<const PPCSubtarget&>"
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"(State.getMachineFunction().getSubtarget()).",
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F),
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A>;
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class CCIfNotSubtarget<string F, CCAction A>
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: CCIf<!strconcat("!static_cast<const PPCSubtarget&>"
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"(State.getMachineFunction().getSubtarget()).",
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F),
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A>;
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//===----------------------------------------------------------------------===//
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// Return Value Calling Convention
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//===----------------------------------------------------------------------===//
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// PPC64 AnyReg return-value convention. No explicit register is specified for
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// the return-value. The register allocator is allowed and expected to choose
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// any free register.
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//
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// This calling convention is currently only supported by the stackmap and
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// patchpoint intrinsics. All other uses will result in an assert on Debug
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// builds. On Release builds we fallback to the PPC C calling convention.
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def RetCC_PPC64_AnyReg : CallingConv<[
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CCCustom<"CC_PPC_AnyReg_Error">
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]>;
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// Return-value convention for PowerPC
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def RetCC_PPC : CallingConv<[
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CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_PPC64_AnyReg>>,
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// On PPC64, integer return values are always promoted to i64
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CCIfType<[i32, i1], CCIfSubtarget<"isPPC64()", CCPromoteToType<i64>>>,
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CCIfType<[i1], CCIfNotSubtarget<"isPPC64()", CCPromoteToType<i32>>>,
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CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
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CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6]>>,
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CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
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// Floating point types returned as "direct" go into F1 .. F8; note that
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// only the ELFv2 ABI fully utilizes all these registers.
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CCIfType<[f32], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
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CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
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// QPX vectors are returned in QF1 and QF2.
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CCIfType<[v4f64, v4f32, v4i1],
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CCIfSubtarget<"hasQPX()", CCAssignToReg<[QF1, QF2]>>>,
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// Vector types returned as "direct" go into V2 .. V9; note that only the
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// ELFv2 ABI fully utilizes all these registers.
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CCIfType<[v16i8, v8i16, v4i32, v4f32], CCIfSubtarget<"hasAltivec()",
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CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>,
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CCIfType<[v2f64, v2i64], CCIfSubtarget<"hasVSX()",
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CCAssignToReg<[VSH2, VSH3, VSH4, VSH5, VSH6, VSH7, VSH8, VSH9]>>>
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]>;
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// No explicit register is specified for the AnyReg calling convention. The
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// register allocator may assign the arguments to any free register.
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//
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// This calling convention is currently only supported by the stackmap and
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// patchpoint intrinsics. All other uses will result in an assert on Debug
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// builds. On Release builds we fallback to the PPC C calling convention.
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def CC_PPC64_AnyReg : CallingConv<[
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CCCustom<"CC_PPC_AnyReg_Error">
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]>;
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// Note that we don't currently have calling conventions for 64-bit
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// PowerPC, but handle all the complexities of the ABI in the lowering
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// logic. FIXME: See if the logic can be simplified with use of CCs.
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// This may require some extensions to current table generation.
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// Simple calling convention for 64-bit ELF PowerPC fast isel.
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// Only handle ints and floats. All ints are promoted to i64.
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// Vector types and quadword ints are not handled.
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def CC_PPC64_ELF_FIS : CallingConv<[
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CCIfCC<"CallingConv::AnyReg", CCDelegateTo<CC_PPC64_AnyReg>>,
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CCIfType<[i1], CCPromoteToType<i64>>,
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CCIfType<[i8], CCPromoteToType<i64>>,
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CCIfType<[i16], CCPromoteToType<i64>>,
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CCIfType<[i32], CCPromoteToType<i64>>,
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CCIfType<[i64], CCAssignToReg<[X3, X4, X5, X6, X7, X8, X9, X10]>>,
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CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>
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]>;
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// Simple return-value convention for 64-bit ELF PowerPC fast isel.
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// All small ints are promoted to i64. Vector types, quadword ints,
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// and multiple register returns are "supported" to avoid compile
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// errors, but none are handled by the fast selector.
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def RetCC_PPC64_ELF_FIS : CallingConv<[
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CCIfCC<"CallingConv::AnyReg", CCDelegateTo<RetCC_PPC64_AnyReg>>,
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CCIfType<[i1], CCPromoteToType<i64>>,
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CCIfType<[i8], CCPromoteToType<i64>>,
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CCIfType<[i16], CCPromoteToType<i64>>,
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CCIfType<[i32], CCPromoteToType<i64>>,
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CCIfType<[i64], CCAssignToReg<[X3, X4]>>,
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CCIfType<[i128], CCAssignToReg<[X3, X4, X5, X6]>>,
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CCIfType<[f32], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
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CCIfType<[f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
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CCIfType<[v4f64, v4f32, v4i1],
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CCIfSubtarget<"hasQPX()", CCAssignToReg<[QF1, QF2]>>>,
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CCIfType<[v16i8, v8i16, v4i32, v4f32], CCIfSubtarget<"hasAltivec()",
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CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9]>>>,
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CCIfType<[v2f64, v2i64], CCIfSubtarget<"hasVSX()",
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CCAssignToReg<[VSH2, VSH3, VSH4, VSH5, VSH6, VSH7, VSH8, VSH9]>>>
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]>;
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//===----------------------------------------------------------------------===//
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// PowerPC System V Release 4 32-bit ABI
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//===----------------------------------------------------------------------===//
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def CC_PPC32_SVR4_Common : CallingConv<[
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CCIfType<[i1], CCPromoteToType<i32>>,
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// The ABI requires i64 to be passed in two adjacent registers with the first
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// register having an odd register number.
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CCIfType<[i32], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignArgRegs">>>,
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// The first 8 integer arguments are passed in integer registers.
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CCIfType<[i32], CCAssignToReg<[R3, R4, R5, R6, R7, R8, R9, R10]>>,
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// Make sure the i64 words from a long double are either both passed in
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// registers or both passed on the stack.
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CCIfType<[f64], CCIfSplit<CCCustom<"CC_PPC32_SVR4_Custom_AlignFPArgRegs">>>,
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// FP values are passed in F1 - F8.
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CCIfType<[f32, f64], CCAssignToReg<[F1, F2, F3, F4, F5, F6, F7, F8]>>,
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// Split arguments have an alignment of 8 bytes on the stack.
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CCIfType<[i32], CCIfSplit<CCAssignToStack<4, 8>>>,
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CCIfType<[i32], CCAssignToStack<4, 4>>,
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// Floats are stored in double precision format, thus they have the same
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// alignment and size as doubles.
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CCIfType<[f32,f64], CCAssignToStack<8, 8>>,
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// QPX vectors that are stored in double precision need 32-byte alignment.
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CCIfType<[v4f64, v4i1], CCAssignToStack<32, 32>>,
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// Vectors get 16-byte stack slots that are 16-byte aligned.
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CCIfType<[v16i8, v8i16, v4i32, v4f32, v2f64, v2i64], CCAssignToStack<16, 16>>
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]>;
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// This calling convention puts vector arguments always on the stack. It is used
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// to assign vector arguments which belong to the variable portion of the
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// parameter list of a variable argument function.
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def CC_PPC32_SVR4_VarArg : CallingConv<[
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CCDelegateTo<CC_PPC32_SVR4_Common>
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]>;
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// In contrast to CC_PPC32_SVR4_VarArg, this calling convention first tries to
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// put vector arguments in vector registers before putting them on the stack.
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def CC_PPC32_SVR4 : CallingConv<[
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// QPX vectors mirror the scalar FP convention.
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CCIfType<[v4f64, v4f32, v4i1], CCIfSubtarget<"hasQPX()",
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CCAssignToReg<[QF1, QF2, QF3, QF4, QF5, QF6, QF7, QF8]>>>,
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// The first 12 Vector arguments are passed in AltiVec registers.
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CCIfType<[v16i8, v8i16, v4i32, v4f32], CCIfSubtarget<"hasAltivec()",
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CCAssignToReg<[V2, V3, V4, V5, V6, V7, V8, V9,
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V10, V11, V12, V13]>>>,
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CCIfType<[v2f64, v2i64], CCIfSubtarget<"hasVSX()",
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CCAssignToReg<[VSH2, VSH3, VSH4, VSH5, VSH6, VSH7, VSH8, VSH9,
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VSH10, VSH11, VSH12, VSH13]>>>,
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CCDelegateTo<CC_PPC32_SVR4_Common>
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]>;
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// Helper "calling convention" to handle aggregate by value arguments.
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// Aggregate by value arguments are always placed in the local variable space
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// of the caller. This calling convention is only used to assign those stack
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// offsets in the callers stack frame.
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//
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// Still, the address of the aggregate copy in the callers stack frame is passed
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// in a GPR (or in the parameter list area if all GPRs are allocated) from the
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// caller to the callee. The location for the address argument is assigned by
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// the CC_PPC32_SVR4 calling convention.
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//
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// The only purpose of CC_PPC32_SVR4_Custom_Dummy is to skip arguments which are
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// not passed by value.
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def CC_PPC32_SVR4_ByVal : CallingConv<[
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CCIfByVal<CCPassByVal<4, 4>>,
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CCCustom<"CC_PPC32_SVR4_Custom_Dummy">
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]>;
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def CSR_Altivec : CalleeSavedRegs<(add V20, V21, V22, V23, V24, V25, V26, V27,
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V28, V29, V30, V31)>;
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def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
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R21, R22, R23, R24, R25, R26, R27, R28,
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R29, R30, R31, F14, F15, F16, F17, F18,
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F19, F20, F21, F22, F23, F24, F25, F26,
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F27, F28, F29, F30, F31, CR2, CR3, CR4
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)>;
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def CSR_Darwin32_Altivec : CalleeSavedRegs<(add CSR_Darwin32, CSR_Altivec)>;
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def CSR_SVR432 : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
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R21, R22, R23, R24, R25, R26, R27, R28,
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R29, R30, R31, F14, F15, F16, F17, F18,
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F19, F20, F21, F22, F23, F24, F25, F26,
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F27, F28, F29, F30, F31, CR2, CR3, CR4
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)>;
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def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>;
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def CSR_Darwin64 : CalleeSavedRegs<(add X13, X14, X15, X16, X17, X18, X19, X20,
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X21, X22, X23, X24, X25, X26, X27, X28,
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X29, X30, X31, F14, F15, F16, F17, F18,
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F19, F20, F21, F22, F23, F24, F25, F26,
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F27, F28, F29, F30, F31, CR2, CR3, CR4
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)>;
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def CSR_Darwin64_Altivec : CalleeSavedRegs<(add CSR_Darwin64, CSR_Altivec)>;
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def CSR_SVR464 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20,
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X21, X22, X23, X24, X25, X26, X27, X28,
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X29, X30, X31, F14, F15, F16, F17, F18,
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F19, F20, F21, F22, F23, F24, F25, F26,
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F27, F28, F29, F30, F31, CR2, CR3, CR4
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)>;
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def CSR_SVR464_Altivec : CalleeSavedRegs<(add CSR_SVR464, CSR_Altivec)>;
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def CSR_SVR464_R2 : CalleeSavedRegs<(add CSR_SVR464, X2)>;
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def CSR_SVR464_R2_Altivec : CalleeSavedRegs<(add CSR_SVR464_Altivec, X2)>;
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def CSR_NoRegs : CalleeSavedRegs<(add)>;
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def CSR_64_AllRegs: CalleeSavedRegs<(add X0, (sequence "X%u", 3, 10),
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(sequence "X%u", 14, 31),
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(sequence "F%u", 0, 31),
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(sequence "CR%u", 0, 7))>;
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def CSR_64_AllRegs_Altivec : CalleeSavedRegs<(add CSR_64_AllRegs,
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(sequence "V%u", 0, 31))>;
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def CSR_64_AllRegs_VSX : CalleeSavedRegs<(add CSR_64_AllRegs_Altivec,
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(sequence "VSL%u", 0, 31),
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(sequence "VSH%u", 0, 31))>;
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