llvm-6502/test/CodeGen/Mips/const6a.ll
Reed Kotler 897473a28d Adjust offsets for max load instruction offsets. This is more pessimistic
than it needs to be by 1 bit but I need to finish some other things so 
that all the boundary cases will work in that situation. constpool.c
in test-suite will fail to assemble under our new internal test-suite sync
without this change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199343 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 00:47:46 +00:00

30 lines
1.3 KiB
LLVM

; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=load-relax1
; RUN: llc -mtriple=mipsel-linux-gnu -march=mipsel -mcpu=mips16 -soft-float -mips16-hard-float -relocation-model=pic -mips16-constant-islands < %s | FileCheck %s -check-prefix=load-relax
; ModuleID = 'const6a.c'
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"
target triple = "mips--linux-gnu"
@i = common global i32 0, align 4
; Function Attrs: nounwind
define void @t() #0 {
entry:
store i32 -559023410, i32* @i, align 4
; load-relax-NOT: lw ${{[0-9]+}}, $CPI0_0 # 16 bit inst
; load-relax1: lw ${{[0-9]+}}, $CPI0_0
; load-relax: jrc $ra
; load-relax: .align 2
; load-relax: $CPI0_0:
; load-relax: .4byte 3735943886
; load-relax: .end t
call void asm sideeffect ".space 10000", ""() #1, !srcloc !1
ret void
}
attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" }
attributes #1 = { nounwind }
!1 = metadata !{i32 121}